1 ;******************************************************************************
2 ;* VP9 IDCT SIMD optimizations
4 ;* Copyright (C) 2013 Clément Bœsch <u pkh me>
5 ;* Copyright (C) 2013 Ronald S. Bultje <rsbultje gmail com>
7 ;* This file is part of FFmpeg.
9 ;* FFmpeg is free software; you can redistribute it and/or
10 ;* modify it under the terms of the GNU Lesser General Public
11 ;* License as published by the Free Software Foundation; either
12 ;* version 2.1 of the License, or (at your option) any later version.
14 ;* FFmpeg is distributed in the hope that it will be useful,
15 ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 ;* Lesser General Public License for more details.
19 ;* You should have received a copy of the GNU Lesser General Public
20 ;* License along with FFmpeg; if not, write to the Free Software
21 ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
22 ;******************************************************************************
24 %include "libavutil/x86/x86util.asm"
28 pw_11585x2: times 8 dw 23170
30 %macro VP9_IDCT_COEFFS 2
31 pw_%1x2: times 8 dw %1*2
32 pw_m%1x2: times 8 dw -%1*2
33 pw_%2x2: times 8 dw %2*2
34 pw_m%2x2: times 8 dw -%2*2
35 pw_m%1_%2: times 4 dw -%1, %2
36 pw_%2_%1: times 4 dw %2, %1
37 pw_m%2_m%1: times 4 dw -%2, -%1
40 VP9_IDCT_COEFFS 15137, 6270
41 VP9_IDCT_COEFFS 16069, 3196
42 VP9_IDCT_COEFFS 9102, 13623
43 VP9_IDCT_COEFFS 16305, 1606
44 VP9_IDCT_COEFFS 10394, 12665
45 VP9_IDCT_COEFFS 14449, 7723
46 VP9_IDCT_COEFFS 4756, 15679
47 VP9_IDCT_COEFFS 16364, 804
48 VP9_IDCT_COEFFS 11003, 12140
49 VP9_IDCT_COEFFS 14811, 7005
50 VP9_IDCT_COEFFS 5520, 15426
51 VP9_IDCT_COEFFS 15893, 3981
52 VP9_IDCT_COEFFS 8423, 14053
53 VP9_IDCT_COEFFS 13160, 9760
54 VP9_IDCT_COEFFS 2404, 16207
56 pd_8192: times 4 dd 8192
57 pw_2048: times 8 dw 2048
58 pw_1024: times 8 dw 1024
59 pw_512: times 8 dw 512
63 ; (a*x + b*y + round) >> shift
64 %macro VP9_MULSUB_2W_2X 5 ; dst1, dst2/src, round, coefs1, coefs2
73 %macro VP9_MULSUB_2W_4X 7 ; dst1, dst2, coef1, coef2, rnd, tmp1/src, tmp2
74 VP9_MULSUB_2W_2X %7, %6, %5, [pw_m%3_%4], [pw_%4_%3]
75 VP9_MULSUB_2W_2X %1, %2, %5, [pw_m%3_%4], [pw_%4_%3]
80 %macro VP9_UNPACK_MULSUB_2W_4X 7-9 ; dst1, dst2, (src1, src2,) coef1, coef2, rnd, tmp1, tmp2
82 punpckhwd m%6, m%2, m%1
84 VP9_MULSUB_2W_4X %1, %2, %3, %4, %5, %6, %7
86 punpckhwd m%8, m%4, m%3
87 punpcklwd m%2, m%4, m%3
88 VP9_MULSUB_2W_4X %1, %2, %5, %6, %7, %8, %9
92 %macro VP9_STORE_2X 5-6 dstq ; reg1, reg2, tmp1, tmp2, zero, dst
94 movh m%4, [%6+strideq]
102 movh [%6+strideq], m%4
105 ;-------------------------------------------------------------------------------------------
106 ; void vp9_idct_idct_4x4_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
107 ;-------------------------------------------------------------------------------------------
109 %macro VP9_IDCT4_1D_FINALIZE 0
110 SUMSUB_BA w, 3, 2, 4 ; m3=t3+t0, m2=-t3+t0
111 SUMSUB_BA w, 1, 0, 4 ; m1=t2+t1, m0=-t2+t1
112 SWAP 0, 3, 2 ; 3102 -> 0123
115 %macro VP9_IDCT4_1D 0
116 SUMSUB_BA w, 2, 0, 4 ; m2=IN(0)+IN(2) m0=IN(0)-IN(2)
117 pmulhrsw m2, m6 ; m2=t0
118 pmulhrsw m0, m6 ; m0=t1
119 VP9_UNPACK_MULSUB_2W_4X 1, 3, 15137, 6270, m7, 4, 5 ; m1=t2, m3=t3
120 VP9_IDCT4_1D_FINALIZE
123 ; 2x2 top left corner
124 %macro VP9_IDCT4_2x2_1D 0
125 pmulhrsw m0, m5 ; m0=t1
128 pmulhrsw m1, m6 ; m1=t2
129 pmulhrsw m3, m7 ; m3=t3
130 VP9_IDCT4_1D_FINALIZE
133 %macro VP9_IDCT4_WRITEOUT 0
135 pmulhrsw m0, m5 ; (x*2048 + (1<<14))>>15 <=> (x+8)>>4
137 VP9_STORE_2X 0, 1, 6, 7, 4
138 lea dstq, [dstq+2*strideq]
141 VP9_STORE_2X 2, 3, 6, 7, 4
145 cglobal vp9_idct_idct_4x4_add, 4,4,0, dst, stride, block, eob
147 cmp eobd, 4 ; 2x2 or smaller
150 cmp eobd, 1 ; faster path for when only DC is set
154 mova m5, [pw_11585x2]
160 pmulhrsw m0, [pw_2048] ; (x*2048 + (1<<14))>>15 <=> (x+8)>>4
161 VP9_STORE_2X 0, 0, 6, 7, 4
162 lea dstq, [dstq+2*strideq]
163 VP9_STORE_2X 0, 0, 6, 7, 4
166 ; faster path for when only top left 2x2 block is set
170 mova m5, [pw_11585x2]
172 mova m7, [pw_15137x2]
174 TRANSPOSE4x4W 0, 1, 2, 3, 4
176 pxor m4, m4 ; used for the block reset, and VP9_STORE_2X
182 .idctfull: ; generic full 4x4 idct/idct
187 mova m6, [pw_11585x2]
188 mova m7, [pd_8192] ; rounding
190 TRANSPOSE4x4W 0, 1, 2, 3, 4
192 pxor m4, m4 ; used for the block reset, and VP9_STORE_2X
200 %if ARCH_X86_64 ; TODO: 32-bit? (32-bit limited to 8 xmm reg, we use more)
202 ;-------------------------------------------------------------------------------------------
203 ; void vp9_idct_idct_8x8_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
204 ;-------------------------------------------------------------------------------------------
206 %macro VP9_IDCT8_1D_FINALIZE 0
207 SUMSUB_BA w, 3, 10, 4 ; m3=t0+t7, m10=t0-t7
208 SUMSUB_BA w, 1, 2, 4 ; m1=t1+t6, m2=t1-t6
209 SUMSUB_BA w, 11, 0, 4 ; m11=t2+t5, m0=t2-t5
210 SUMSUB_BA w, 9, 8, 4 ; m9=t3+t4, m8=t3-t4
215 %macro VP9_IDCT8_1D 0
216 SUMSUB_BA w, 8, 0, 4 ; m8=IN(0)+IN(4) m0=IN(0)-IN(4)
217 pmulhrsw m8, m12 ; m8=t0a
218 pmulhrsw m0, m12 ; m0=t1a
219 VP9_UNPACK_MULSUB_2W_4X 2, 10, 15137, 6270, m7, 4, 5 ; m2=t2a, m10=t3a
220 VP9_UNPACK_MULSUB_2W_4X 1, 11, 16069, 3196, m7, 4, 5 ; m1=t4a, m11=t7a
221 VP9_UNPACK_MULSUB_2W_4X 9, 3, 9102, 13623, m7, 4, 5 ; m9=t5a, m3=t6a
222 SUMSUB_BA w, 10, 8, 4 ; m10=t0a+t3a (t0), m8=t0a-t3a (t3)
223 SUMSUB_BA w, 2, 0, 4 ; m2=t1a+t2a (t1), m0=t1a-t2a (t2)
224 SUMSUB_BA w, 9, 1, 4 ; m9=t4a+t5a (t4), m1=t4a-t5a (t5a)
225 SUMSUB_BA w, 3, 11, 4 ; m3=t7a+t6a (t7), m11=t7a-t6a (t6a)
226 SUMSUB_BA w, 1, 11, 4 ; m1=t6a+t5a (t6), m11=t6a-t5a (t5)
227 pmulhrsw m1, m12 ; m1=t6
228 pmulhrsw m11, m12 ; m11=t5
229 VP9_IDCT8_1D_FINALIZE
232 %macro VP9_IDCT8_4x4_1D 0
233 pmulhrsw m0, m12 ; m0=t1a/t0a
234 pmulhrsw m10, m2, [pw_15137x2] ; m10=t3a
235 pmulhrsw m2, [pw_6270x2] ; m2=t2a
236 pmulhrsw m11, m1, [pw_16069x2] ; m11=t7a
237 pmulhrsw m1, [pw_3196x2] ; m1=t4a
238 pmulhrsw m9, m3, [pw_9102x2] ; m9=-t5a
239 pmulhrsw m3, [pw_13623x2] ; m3=t6a
240 psubw m8, m0, m10 ; m8=t0a-t3a (t3)
241 paddw m10, m0 ; m10=t0a+t3a (t0)
242 SUMSUB_BA w, 2, 0, 4 ; m2=t1a+t2a (t1), m0=t1a-t2a (t2)
243 SUMSUB_BA w, 9, 1, 4 ; m1=t4a+t5a (t4), m9=t4a-t5a (t5a)
245 SUMSUB_BA w, 3, 11, 4 ; m3=t7a+t6a (t7), m11=t7a-t6a (t6a)
246 SUMSUB_BA w, 1, 11, 4 ; m1=t6a+t5a (t6), m11=t6a-t5a (t5)
247 pmulhrsw m1, m12 ; m1=t6
248 pmulhrsw m11, m12 ; m11=t5
249 VP9_IDCT8_1D_FINALIZE
252 ; TODO: a lot of t* copies can probably be removed and merged with
253 ; following SUMSUBs from VP9_IDCT8_1D_FINALIZE with AVX
254 %macro VP9_IDCT8_2x2_1D 0
255 pmulhrsw m0, m12 ; m0=t0
257 pmulhrsw m1, m6 ; m1=t4
258 pmulhrsw m3, m7 ; m3=t7
260 mova m10, m0 ; m10=t2
262 mova m11, m3 ; t5 = t7a ...
263 mova m9, m3 ; t6 = t7a ...
264 psubw m11, m1 ; t5 = t7a - t4a
265 paddw m9, m1 ; t6 = t7a + t4a
266 pmulhrsw m11, m12 ; m11=t5
267 pmulhrsw m9, m12 ; m9=t6
270 VP9_IDCT8_1D_FINALIZE
273 %macro VP9_IDCT8_WRITEOUT 0
275 pmulhrsw m0, m5 ; (x*1024 + (1<<14))>>15 <=> (x+16)>>5
277 VP9_STORE_2X 0, 1, 6, 7, 4
278 lea dstq, [dstq+2*strideq]
281 VP9_STORE_2X 2, 3, 6, 7, 4
282 lea dstq, [dstq+2*strideq]
285 VP9_STORE_2X 8, 9, 6, 7, 4
286 lea dstq, [dstq+2*strideq]
289 VP9_STORE_2X 10, 11, 6, 7, 4
292 %macro VP9_IDCT_IDCT_8x8_ADD_XMM 1
294 cglobal vp9_idct_idct_8x8_add, 4,4,13, dst, stride, block, eob
296 mova m12, [pw_11585x2] ; often used
298 cmp eobd, 12 ; top left half or less
301 cmp eobd, 3 ; top left corner or less
304 cmp eobd, 1 ; faster path for when only DC is set
305 jne .idcttopleftcorner
314 pmulhrsw m0, m5 ; (x*1024 + (1<<14))>>15 <=> (x+16)>>5
315 VP9_STORE_2X 0, 0, 6, 7, 4
316 lea dstq, [dstq+2*strideq]
317 VP9_STORE_2X 0, 0, 6, 7, 4
318 lea dstq, [dstq+2*strideq]
319 VP9_STORE_2X 0, 0, 6, 7, 4
320 lea dstq, [dstq+2*strideq]
321 VP9_STORE_2X 0, 0, 6, 7, 4
324 ; faster path for when only left corner is set (3 input: DC, right to DC, below
325 ; to DC). Note: also working with a 2x2 block
330 mova m7, [pw_16069x2]
332 TRANSPOSE8x8W 0, 1, 2, 3, 8, 9, 10, 11, 4
334 pxor m4, m4 ; used for the block reset, and VP9_STORE_2X
341 movh m0, [blockq + 0]
342 movh m1, [blockq +16]
343 movh m2, [blockq +32]
344 movh m3, [blockq +48]
346 TRANSPOSE8x8W 0, 1, 2, 3, 8, 9, 10, 11, 4
356 .idctfull: ; generic full 8x8 idct/idct
357 mova m0, [blockq+ 0] ; IN(0)
358 mova m1, [blockq+ 16] ; IN(1)
359 mova m2, [blockq+ 32] ; IN(2)
360 mova m3, [blockq+ 48] ; IN(3)
361 mova m8, [blockq+ 64] ; IN(4)
362 mova m9, [blockq+ 80] ; IN(5)
363 mova m10, [blockq+ 96] ; IN(6)
364 mova m11, [blockq+112] ; IN(7)
365 mova m7, [pd_8192] ; rounding
367 TRANSPOSE8x8W 0, 1, 2, 3, 8, 9, 10, 11, 4
369 pxor m4, m4 ; used for the block reset, and VP9_STORE_2X
371 mova [blockq+ 16], m4
372 mova [blockq+ 32], m4
373 mova [blockq+ 48], m4
374 mova [blockq+ 64], m4
375 mova [blockq+ 80], m4
376 mova [blockq+ 96], m4
377 mova [blockq+112], m4
382 VP9_IDCT_IDCT_8x8_ADD_XMM ssse3
383 VP9_IDCT_IDCT_8x8_ADD_XMM avx
385 ;---------------------------------------------------------------------------------------------
386 ; void vp9_idct_idct_16x16_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
387 ;---------------------------------------------------------------------------------------------
389 ; at the end of this macro, m7 is stored in stack_scratch
390 ; everything else (t0-6 and t8-15) is stored in m0-6 and m8-15
391 ; the following sumsubs have not been done yet:
392 ; SUMSUB_BA w, 6, 9, 15 ; t6, t9
393 ; SUMSUB_BA w, 7, 8, 15 ; t7, t8
394 %macro VP9_IDCT16_1D_START 4 ; src, nnzc, stride, stack_scratch
396 mova m3, [%1+ 1*%3] ; IN(1)
397 mova m12, [%1+ 2*%3] ; IN(2)
398 mova m0, [%1+ 3*%3] ; IN(3)
400 pmulhrsw m15, m12, [pw_16069x2] ; t6-7
401 pmulhrsw m12, [pw_3196x2] ; t4-5
402 pmulhrsw m4, m3, [pw_16305x2] ; t14-15
403 pmulhrsw m3, [pw_1606x2] ; t8-9
404 pmulhrsw m7, m0, [pw_m4756x2] ; t10-11
405 pmulhrsw m0, [pw_15679x2] ; t12-13
407 ; m8=t0, m9=t1, m10=t2, m11=t3, m12=t4, m14=t5, m13=t6, m15=t7
408 ; m3=t8, m5=t9, m1=t10, m7=t11, m0=t12, m6=t13, m2=t14, m4=t15
412 pmulhrsw m13, [pw_11585x2] ; t5
413 pmulhrsw m14, [pw_11585x2] ; t6
415 VP9_UNPACK_MULSUB_2W_4X 2, 5, 4, 3, 15137, 6270, [pd_8192], 10, 11 ; t9, t14
416 VP9_UNPACK_MULSUB_2W_4X 6, 1, 0, 7, 6270, m15137, [pd_8192], 10, 11 ; t10, t13
418 ; m15=t0, m14=t1, m13=t2, m12=t3, m11=t4, m10=t5, m9=t6, m8=t7
419 ; m7=t8, m6=t9, m2=t10, m3=t11, m4=t12, m5=t13, m1=t14, m0=t15
421 mova m5, [%1+ 1*%3] ; IN(1)
422 mova m14, [%1+ 2*%3] ; IN(2)
423 mova m6, [%1+ 3*%3] ; IN(3)
424 mova m9, [%1+ 4*%3] ; IN(4)
425 mova m7, [%1+ 5*%3] ; IN(5)
426 mova m15, [%1+ 6*%3] ; IN(6)
427 mova m4, [%1+ 7*%3] ; IN(7)
429 pmulhrsw m8, m9, [pw_15137x2] ; t3
430 pmulhrsw m9, [pw_6270x2] ; t2
431 pmulhrsw m13, m14, [pw_16069x2] ; t7
432 pmulhrsw m14, [pw_3196x2] ; t4
433 pmulhrsw m12, m15, [pw_m9102x2] ; t5
434 pmulhrsw m15, [pw_13623x2] ; t6
435 pmulhrsw m2, m5, [pw_16305x2] ; t15
436 pmulhrsw m5, [pw_1606x2] ; t8
437 pmulhrsw m3, m4, [pw_m10394x2] ; t9
438 pmulhrsw m4, [pw_12665x2] ; t14
439 pmulhrsw m0, m7, [pw_14449x2] ; t13
440 pmulhrsw m7, [pw_7723x2] ; t10
441 pmulhrsw m1, m6, [pw_m4756x2] ; t11
442 pmulhrsw m6, [pw_15679x2] ; t12
444 mova m3, [%1+ 9*%3] ; IN(9)
445 mova m12, [%1+10*%3] ; IN(10)
446 mova m0, [%1+11*%3] ; IN(11)
447 mova m8, [%1+12*%3] ; IN(12)
448 mova m1, [%1+13*%3] ; IN(13)
449 mova m13, [%1+14*%3] ; IN(14)
450 mova m2, [%1+15*%3] ; IN(15)
452 ; m10=in0, m5=in1, m14=in2, m6=in3, m9=in4, m7=in5, m15=in6, m4=in7
453 ; m11=in8, m3=in9, m12=in10 m0=in11, m8=in12, m1=in13, m13=in14, m2=in15
455 VP9_UNPACK_MULSUB_2W_4X 9, 8, 15137, 6270, [pd_8192], 10, 11 ; t2, t3
456 VP9_UNPACK_MULSUB_2W_4X 14, 13, 16069, 3196, [pd_8192], 10, 11 ; t4, t7
457 VP9_UNPACK_MULSUB_2W_4X 12, 15, 9102, 13623, [pd_8192], 10, 11 ; t5, t6
458 VP9_UNPACK_MULSUB_2W_4X 5, 2, 16305, 1606, [pd_8192], 10, 11 ; t8, t15
459 VP9_UNPACK_MULSUB_2W_4X 3, 4, 10394, 12665, [pd_8192], 10, 11 ; t9, t14
460 VP9_UNPACK_MULSUB_2W_4X 7, 0, 14449, 7723, [pd_8192], 10, 11 ; t10, t13
461 VP9_UNPACK_MULSUB_2W_4X 1, 6, 4756, 15679, [pd_8192], 10, 11 ; t11, t12
464 ; m11=t0, m10=t1, m9=t2, m8=t3, m14=t4, m12=t5, m15=t6, m13=t7
465 ; m5=t8, m3=t9, m7=t10, m1=t11, m6=t12, m0=t13, m4=t14, m2=t15
467 SUMSUB_BA w, 12, 14, 10 ; t4, t5
468 SUMSUB_BA w, 15, 13, 10 ; t7, t6
469 SUMSUB_BA w, 3, 5, 10 ; t8, t9
470 SUMSUB_BA w, 7, 1, 10 ; t11, t10
471 SUMSUB_BA w, 0, 6, 10 ; t12, t13
472 SUMSUB_BA w, 4, 2, 10 ; t15, t14
474 ; m8=t0, m9=t1, m10=t2, m11=t3, m12=t4, m14=t5, m13=t6, m15=t7
475 ; m3=t8, m5=t9, m1=t10, m7=t11, m0=t12, m6=t13, m2=t14, m4=t15
477 SUMSUB_BA w, 14, 13, 10
478 pmulhrsw m13, [pw_11585x2] ; t5
479 pmulhrsw m14, [pw_11585x2] ; t6
480 VP9_UNPACK_MULSUB_2W_4X 2, 5, 15137, 6270, [pd_8192], 10, 11 ; t9, t14
481 VP9_UNPACK_MULSUB_2W_4X 6, 1, 6270, m15137, [pd_8192], 10, 11 ; t10, t13
484 ; m8=t0, m9=t1, m10=t2, m11=t3, m12=t4, m13=t5, m14=t6, m15=t7
485 ; m3=t8, m2=t9, m6=t10, m7=t11, m0=t12, m1=t13, m5=t14, m4=t15
487 SUMSUB_BA w, 7, 3, 10 ; t8, t11
488 SUMSUB_BA w, 6, 2, 10 ; t9, t10
489 SUMSUB_BA w, 0, 4, 10 ; t15, t12
490 SUMSUB_BA w, 1, 5, 10 ; t14. t13
492 ; m15=t0, m14=t1, m13=t2, m12=t3, m11=t4, m10=t5, m9=t6, m8=t7
493 ; m7=t8, m6=t9, m2=t10, m3=t11, m4=t12, m5=t13, m1=t14, m0=t15
495 SUMSUB_BA w, 2, 5, 10
496 SUMSUB_BA w, 3, 4, 10
497 pmulhrsw m5, [pw_11585x2] ; t10
498 pmulhrsw m4, [pw_11585x2] ; t11
499 pmulhrsw m3, [pw_11585x2] ; t12
500 pmulhrsw m2, [pw_11585x2] ; t13
502 ; backup first register
505 ; m15=t0, m14=t1, m13=t2, m12=t3, m11=t4, m10=t5, m9=t6, m8=t7
506 ; m7=t8, m6=t9, m5=t10, m4=t11, m3=t12, m2=t13, m1=t14, m0=t15
510 mova m11, [%1+ 0*%3] ; IN(0)
511 pmulhrsw m11, [pw_11585x2] ; t0-t3
520 mova m10, [%1+ 0*%3] ; IN(0)
522 pmulhrsw m10, [pw_11585x2] ; t0 and t1
526 mova m11, [%1+ 8*%3] ; IN(8)
529 SUMSUB_BA w, 11, 10, 7
530 pmulhrsw m11, [pw_11585x2] ; t0
531 pmulhrsw m10, [pw_11585x2] ; t1
534 SUMSUB_BA w, 8, 11, 7 ; t0, t3
536 SUMSUB_BA w, 9, 10, 7 ; t1, t2
539 SUMSUB_BA w, 15, 8, 7 ; t0, t7
540 SUMSUB_BA w, 14, 9, 7 ; t1, t6
541 SUMSUB_BA w, 13, 10, 7 ; t2, t5
543 SUMSUB_BA w, 12, 11, 7 ; t3, t4
545 SUMSUB_BA w, 0, 15, 7 ; t0, t15
546 SUMSUB_BA w, 1, 14, 7 ; t1, t14
547 SUMSUB_BA w, 2, 13, 7 ; t2, t13
548 SUMSUB_BA w, 3, 12, 7 ; t3, t12
549 SUMSUB_BA w, 4, 11, 7 ; t4, t11
550 SUMSUB_BA w, 5, 10, 7 ; t5, t10
553 %macro VP9_IDCT16_1D 2-3 16 ; src, pass, nnzc
554 VP9_IDCT16_1D_START %1, %3, 32, rsp+32
557 ; backup a different register
561 SUMSUB_BA w, 6, 9, 15 ; t6, t9
562 SUMSUB_BA w, 7, 8, 15 ; t7, t8
564 TRANSPOSE8x8W 0, 1, 2, 3, 4, 5, 6, 7, 15
575 TRANSPOSE8x8W 8, 9, 10, 11, 12, 13, 14, 15, 0
585 ; backup more registers
590 pmulhrsw m0, [pw_512]
591 pmulhrsw m1, [pw_512]
592 VP9_STORE_2X 0, 1, 8, 9, 7
593 lea dstq, [dstq+strideq*2]
594 pmulhrsw m2, [pw_512]
595 pmulhrsw m3, [pw_512]
596 VP9_STORE_2X 2, 3, 8, 9, 7
597 lea dstq, [dstq+strideq*2]
598 pmulhrsw m4, [pw_512]
599 pmulhrsw m5, [pw_512]
600 VP9_STORE_2X 4, 5, 8, 9, 7
601 lea dstq, [dstq+strideq*2]
604 SWAP 0, 7 ; move zero from m7 to m0
609 SUMSUB_BA w, 6, 9, 1 ; t6, t9
610 SUMSUB_BA w, 7, 8, 1 ; t7, t8
612 pmulhrsw m6, [pw_512]
613 pmulhrsw m7, [pw_512]
614 VP9_STORE_2X 6, 7, 1, 2, 0
615 lea dstq, [dstq+strideq*2]
616 pmulhrsw m8, [pw_512]
617 pmulhrsw m9, [pw_512]
618 VP9_STORE_2X 8, 9, 1, 2, 0
619 lea dstq, [dstq+strideq*2]
620 pmulhrsw m10, [pw_512]
621 pmulhrsw m11, [pw_512]
622 VP9_STORE_2X 10, 11, 1, 2, 0
623 lea dstq, [dstq+strideq*2]
624 pmulhrsw m12, [pw_512]
625 pmulhrsw m13, [pw_512]
626 VP9_STORE_2X 12, 13, 1, 2, 0
627 lea dstq, [dstq+strideq*2]
628 pmulhrsw m14, [pw_512]
629 pmulhrsw m15, [pw_512]
630 VP9_STORE_2X 14, 15, 1, 2, 0
634 %macro ZERO_BLOCK 4 ; mem, stride, nnzcpl, zero_reg
639 mova [%1+%%y+%%x], %4
640 %assign %%x (%%x+mmsize)
646 %macro VP9_STORE_2XFULL 6-7 strideq; dc, tmp1, tmp2, tmp3, tmp4, zero, stride
649 punpcklbw m%2, m%3, m%6
651 punpcklbw m%4, m%5, m%6
663 %macro VP9_IDCT_IDCT_16x16_ADD_XMM 1
665 cglobal vp9_idct_idct_16x16_add, 4, 5, 16, 512, dst, stride, block, eob
666 ; 2x2=eob=3, 4x4=eob=10
669 cmp eobd, 1 ; faster path for when only DC is set
674 mova m1, [pw_11585x2]
678 pmulhrsw m0, [pw_512]
682 VP9_STORE_2XFULL 0, 1, 2, 3, 4, 5
683 lea dstq, [dstq+2*strideq]
685 VP9_STORE_2XFULL 0, 1, 2, 3, 4, 5
689 DEFINE_ARGS dst, stride, block, cnt, dst_bak
690 VP9_IDCT16_1D blockq, 1, 8
695 VP9_IDCT16_1D rsp, 2, 8
696 lea dstq, [dst_bakq+8]
702 ; at the end of the loop, m0 should still be zero
703 ; use that to zero out block coefficients
704 ZERO_BLOCK blockq, 32, 8, m0
708 DEFINE_ARGS dst, stride, block, cnt, dst_bak
711 VP9_IDCT16_1D blockq, 1
723 lea dstq, [dst_bakq+8]
729 ; at the end of the loop, m0 should still be zero
730 ; use that to zero out block coefficients
731 ZERO_BLOCK blockq, 32, 16, m0
735 VP9_IDCT_IDCT_16x16_ADD_XMM ssse3
736 VP9_IDCT_IDCT_16x16_ADD_XMM avx
738 ;---------------------------------------------------------------------------------------------
739 ; void vp9_idct_idct_32x32_add_<opt>(uint8_t *dst, ptrdiff_t stride, int16_t *block, int eob);
740 ;---------------------------------------------------------------------------------------------
742 %macro VP9_IDCT32_1D 2-3 32 ; src, pass, nnzc
743 %assign %%str 16*%2*%2
744 ; first do t0-15, this can be done identical to idct16x16
745 VP9_IDCT16_1D_START %1, %3/2, 64*2, rsp+ 4*%%str
747 ; backup a different register
748 mova [rsp+30*%%str], m15 ; t15
749 mova m7, [rsp+ 4*%%str]
751 SUMSUB_BA w, 6, 9, 15 ; t6, t9
752 SUMSUB_BA w, 7, 8, 15 ; t7, t8
754 ; store everything on stack to make space available for t16-31
755 ; we store interleaved with the output of the second half (t16-31)
756 ; so we don't need to allocate extra stack space
757 mova [rsp+ 0*%%str], m0 ; t0
758 mova [rsp+ 4*%%str], m1 ; t1
759 mova [rsp+ 8*%%str], m2 ; t2
760 mova [rsp+12*%%str], m3 ; t3
761 mova [rsp+16*%%str], m4 ; t4
762 mova [rsp+20*%%str], m5 ; t5
763 mova [rsp+24*%%str], m6 ; t6
764 mova [rsp+28*%%str], m7 ; t7
765 mova [rsp+ 2*%%str], m8 ; t8
766 mova [rsp+ 6*%%str], m9 ; t9
767 mova [rsp+10*%%str], m10 ; t10
768 mova [rsp+14*%%str], m11 ; t11
769 mova [rsp+18*%%str], m12 ; t12
770 mova [rsp+22*%%str], m13 ; t13
771 mova [rsp+26*%%str], m14 ; t14
773 ; then, secondly, do t16-31
780 pmulhrsw m11, m4, [pw_16364x2] ;t31
781 pmulhrsw m4, [pw_804x2] ;t16
782 pmulhrsw m8, m7, [pw_m5520x2] ;t19
783 pmulhrsw m7, [pw_15426x2] ;t28
784 pmulhrsw m15, m0, [pw_15893x2] ;t27
785 pmulhrsw m0, [pw_3981x2] ;t20
786 pmulhrsw m12, m3, [pw_m2404x2] ;t23
787 pmulhrsw m3, [pw_16207x2] ;t24
789 ; m4=t16/17, m8=t18/19, m0=t20/21, m12=t22/23,
790 ; m3=t24/25, m15=t26/27, m7=t28/29, m11=t30/31
792 VP9_UNPACK_MULSUB_2W_4X 5, 10, 11, 4, 16069, 3196, [pd_8192], 6, 9 ; t17, t30
793 VP9_UNPACK_MULSUB_2W_4X 9, 6, 7, 8, 3196, m16069, [pd_8192], 1, 14 ; t18, t29
794 ; from 1 stage forward
797 mova [rsp+17*%%str], m8 ; t16
798 mova [rsp+21*%%str], m4 ; t19
799 VP9_UNPACK_MULSUB_2W_4X 1, 14, 15, 0, 9102, 13623, [pd_8192], 4, 8 ; t21, t26
800 VP9_UNPACK_MULSUB_2W_4X 13, 2, 3, 12, 13623, m9102, [pd_8192], 4, 8 ; t22, t25
802 ; m4=t16, m5=t17, m9=t18, m8=t19, m0=t20, m1=t21, m13=t22, m12=t23,
803 ; m3=t24, m2=t25, m14=t26, m15=t27, m7=t28, m6=t29, m10=t30, m11=t31
814 pmulhrsw m5, m10, [pw_16364x2]
815 pmulhrsw m10, [pw_804x2]
816 pmulhrsw m4, m11, [pw_m11003x2]
817 pmulhrsw m11, [pw_12140x2]
818 pmulhrsw m7, m8, [pw_14811x2]
819 pmulhrsw m8, [pw_7005x2]
820 pmulhrsw m6, m9, [pw_m5520x2]
821 pmulhrsw m9, [pw_15426x2]
822 pmulhrsw m1, m14, [pw_15893x2]
823 pmulhrsw m14, [pw_3981x2]
824 pmulhrsw m0, m15, [pw_m8423x2]
825 pmulhrsw m15, [pw_14053x2]
834 ; m10=in1, m4=in17, m8=in9, m6=in25, m14=in5, m0=in21, m12=in13, m2=in29,
835 ; m13=in3, m3=in19, m15=in11, m1=in27, m9=in7, m7=in23, m11=in15, m5=in31
837 VP9_UNPACK_MULSUB_2W_4X 10, 5, 16364, 804, [pd_8192], 2, 3 ; t16, t31
838 VP9_UNPACK_MULSUB_2W_4X 4, 11, 11003, 12140, [pd_8192], 2, 3 ; t17, t30
839 VP9_UNPACK_MULSUB_2W_4X 8, 7, 14811, 7005, [pd_8192], 2, 3 ; t18, t29
840 VP9_UNPACK_MULSUB_2W_4X 6, 9, 5520, 15426, [pd_8192], 2, 3 ; t19, t28
841 VP9_UNPACK_MULSUB_2W_4X 14, 1, 15893, 3981, [pd_8192], 2, 3 ; t20, t27
842 VP9_UNPACK_MULSUB_2W_4X 0, 15, 8423, 14053, [pd_8192], 2, 3 ; t21, t26
845 ; from 1 stage forward
846 SUMSUB_BA w, 4, 10, 2
848 ; from 2 stages forward
851 mova [rsp+17*%%str], m8 ; t16
852 mova [rsp+21*%%str], m4 ; t19
854 pmulhrsw m3, m12, [pw_13160x2]
855 pmulhrsw m12, [pw_9760x2]
856 pmulhrsw m2, m13, [pw_m2404x2]
857 pmulhrsw m13, [pw_16207x2]
861 VP9_UNPACK_MULSUB_2W_4X 12, 3, 13160, 9760, [pd_8192], 4, 8 ; t22, t25
862 VP9_UNPACK_MULSUB_2W_4X 2, 13, 2404, 16207, [pd_8192], 4, 8 ; t23, t24
865 ; m10=t16, m4=t17, m8=t18, m6=t19, m14=t20, m0=t21, m12=t22, m2=t23,
866 ; m13=t24, m3=t25, m15=t26, m1=t27, m9=t28, m7=t29, m11=t30, m5=t31
868 SUMSUB_BA w, 0, 14, 4
869 SUMSUB_BA w, 12, 2, 4
870 SUMSUB_BA w, 3, 13, 4
871 SUMSUB_BA w, 15, 1, 4
873 SUMSUB_BA w, 11, 5, 4
875 ; m4=t16, m10=t17, m6=t18, m8=t19, m0=t20, m14=t21, m2=t22, m12=t23,
876 ; m3=t24, m13=t25, m1=t26, m15=t27, m7=t28, m9=t29, m5=t30, m11=t31
878 VP9_UNPACK_MULSUB_2W_4X 5, 10, 16069, 3196, [pd_8192], 4, 8 ; t17, t30
879 VP9_UNPACK_MULSUB_2W_4X 9, 6, 3196, m16069, [pd_8192], 4, 8 ; t18, t29
880 VP9_UNPACK_MULSUB_2W_4X 1, 14, 9102, 13623, [pd_8192], 4, 8 ; t21, t26
881 VP9_UNPACK_MULSUB_2W_4X 13, 2, 13623, m9102, [pd_8192], 4, 8 ; t22, t25
884 ; m4=t16, m5=t17, m9=t18, m8=t19, m0=t20, m1=t21, m13=t22, m12=t23,
885 ; m3=t24, m2=t25, m14=t26, m15=t27, m7=t28, m6=t29, m10=t30, m11=t31
888 SUMSUB_BA w, 1, 13, 4
889 SUMSUB_BA w, 0, 12, 4
890 SUMSUB_BA w, 15, 3, 4
891 SUMSUB_BA w, 14, 2, 4
892 SUMSUB_BA w, 6, 10, 4
893 SUMSUB_BA w, 7, 11, 4
895 ; m8[s]=t16, m9=t17, m5=t18, m4[s]=t19, m12=t20, m13=t21, m1=t22, m0=t23,
896 ; m15=t24, m14=t25, m2=t26, m3=t27, m11=t28, m10=t29, m6=t30, m7=t31
898 mova m8, [rsp+17*%%str] ; t16
899 ; from 2 stages forward
901 SUMSUB_BA w, 15, 7, 4
902 ; from 3 stages forward
904 pmulhrsw m7, [pw_11585x2]
905 pmulhrsw m8, [pw_11585x2]
907 mova [rsp+ 1*%%str], m0 ; t16
908 mova [rsp+29*%%str], m7 ; t23
910 mova m4, [rsp+21*%%str] ; t19
911 VP9_UNPACK_MULSUB_2W_4X 10, 5, 15137, 6270, [pd_8192], 0, 7 ; t18, t29
912 VP9_UNPACK_MULSUB_2W_4X 11, 4, 15137, 6270, [pd_8192], 0, 7 ; t19, t28
913 VP9_UNPACK_MULSUB_2W_4X 3, 12, 6270, m15137, [pd_8192], 0, 7 ; t20, t27
914 VP9_UNPACK_MULSUB_2W_4X 2, 13, 6270, m15137, [pd_8192], 0, 7 ; t21, t26
916 ; m8=t16, m9=t17, m10=t18, m11=t19, m3=t20, m2=t21, m1=t22, m0=t23,
917 ; m15=t24, m14=t25, m13=t26, m12=t27, m4=t28, m5=t29, m6=t30, m7=t31
920 SUMSUB_BA w, 2, 10, 0
921 SUMSUB_BA w, 3, 11, 0
922 SUMSUB_BA w, 12, 4, 0
923 SUMSUB_BA w, 13, 5, 0
924 SUMSUB_BA w, 14, 6, 0
926 ; m0=t16, m1=t17, m2=t18, m3=t19, m11=t20, m10=t21, m9=t22, m8=t23,
927 ; m7=t24, m6=t25, m5=t26, m4=t27, m12=t28, m13=t29, m14=t30, m15=t31
930 SUMSUB_BA w, 10, 5, 0
931 SUMSUB_BA w, 11, 4, 0
933 pmulhrsw m6, [pw_11585x2]
934 pmulhrsw m9, [pw_11585x2]
935 pmulhrsw m5, [pw_11585x2]
936 pmulhrsw m10, [pw_11585x2]
937 pmulhrsw m4, [pw_11585x2]
938 pmulhrsw m11, [pw_11585x2]
940 ; m0=t16, m1=t17, m2=t18, m3=t19, m4=t20, m5=t21, m6=t22, m7=t23,
941 ; m8=t24, m9=t25, m10=t26, m11=t27, m12=t28, m13=t29, m14=t30, m15=t31
943 ; store t17-19 (and t20-22 for pass 1) - keep t24-31 in registers for
944 ; final sumsub in pass 1, or keep t20-22 and t24-31 in registers for
945 ; final sumsub of pass 2
946 mova [rsp+ 5*%%str], m1 ; t17
947 mova [rsp+ 9*%%str], m2 ; t18
948 mova [rsp+13*%%str], m3 ; t19
950 ; then do final pass to sumsub+store the two halves
952 mova [rsp+17*%%str], m4 ; t20
953 mova [rsp+21*%%str], m5 ; t21
954 mova [rsp+25*%%str], m6 ; t22
956 mova m0, [rsp+ 0*%%str] ; t0
957 mova m1, [rsp+ 4*%%str] ; t1
958 mova m2, [rsp+ 8*%%str] ; t2
959 mova m3, [rsp+12*%%str] ; t3
960 mova m4, [rsp+16*%%str] ; t4
961 mova m5, [rsp+20*%%str] ; t5
962 mova m6, [rsp+24*%%str] ; t6
964 SUMSUB_BA w, 15, 0, 7
965 mova [rsp+ 3*%%str], m0 ; t15
966 mova m7, [rsp+28*%%str] ; t7
967 SUMSUB_BA w, 14, 1, 0
968 SUMSUB_BA w, 13, 2, 0
969 SUMSUB_BA w, 12, 3, 0
970 SUMSUB_BA w, 11, 4, 0
971 SUMSUB_BA w, 10, 5, 0
975 TRANSPOSE8x8W 15, 14, 13, 12, 11, 10, 9, 8, 0
976 mova [rsp+ 0*%%str], m15
977 mova [rsp+ 4*%%str], m14
978 mova [rsp+ 8*%%str], m13
979 mova [rsp+12*%%str], m12
980 mova [rsp+16*%%str], m11
981 mova [rsp+20*%%str], m10
982 mova [rsp+24*%%str], m9
983 mova [rsp+28*%%str], m8
985 mova m0, [rsp+ 3*%%str] ; t15
986 TRANSPOSE8x8W 7, 6, 5, 4, 3, 2, 1, 0, 8
987 mova [rsp+ 3*%%str], m7
988 mova [rsp+ 7*%%str], m6
989 mova [rsp+11*%%str], m5
990 mova [rsp+15*%%str], m4
991 mova [rsp+19*%%str], m3
992 mova [rsp+23*%%str], m2
993 mova [rsp+27*%%str], m1
994 mova [rsp+31*%%str], m0
996 mova m15, [rsp+ 2*%%str] ; t8
997 mova m14, [rsp+ 6*%%str] ; t9
998 mova m13, [rsp+10*%%str] ; t10
999 mova m12, [rsp+14*%%str] ; t11
1000 mova m11, [rsp+18*%%str] ; t12
1001 mova m10, [rsp+22*%%str] ; t13
1002 mova m9, [rsp+26*%%str] ; t14
1003 mova m8, [rsp+30*%%str] ; t15
1004 mova m7, [rsp+ 1*%%str] ; t16
1005 mova m6, [rsp+ 5*%%str] ; t17
1006 mova m5, [rsp+ 9*%%str] ; t18
1007 mova m4, [rsp+13*%%str] ; t19
1008 mova m3, [rsp+17*%%str] ; t20
1009 mova m2, [rsp+21*%%str] ; t21
1010 mova m1, [rsp+25*%%str] ; t22
1012 SUMSUB_BA w, 7, 8, 0
1013 mova [rsp+ 2*%%str], m8
1014 mova m0, [rsp+29*%%str] ; t23
1015 SUMSUB_BA w, 6, 9, 8
1016 SUMSUB_BA w, 5, 10, 8
1017 SUMSUB_BA w, 4, 11, 8
1018 SUMSUB_BA w, 3, 12, 8
1019 SUMSUB_BA w, 2, 13, 8
1020 SUMSUB_BA w, 1, 14, 8
1021 SUMSUB_BA w, 0, 15, 8
1023 TRANSPOSE8x8W 0, 1, 2, 3, 4, 5, 6, 7, 8
1024 mova [rsp+ 1*%%str], m0
1025 mova [rsp+ 5*%%str], m1
1026 mova [rsp+ 9*%%str], m2
1027 mova [rsp+13*%%str], m3
1028 mova [rsp+17*%%str], m4
1029 mova [rsp+21*%%str], m5
1030 mova [rsp+25*%%str], m6
1031 mova [rsp+29*%%str], m7
1033 mova m8, [rsp+ 2*%%str]
1034 TRANSPOSE8x8W 8, 9, 10, 11, 12, 13, 14, 15, 0
1035 mova [rsp+ 2*%%str], m8
1036 mova [rsp+ 6*%%str], m9
1037 mova [rsp+10*%%str], m10
1038 mova [rsp+14*%%str], m11
1039 mova [rsp+18*%%str], m12
1040 mova [rsp+22*%%str], m13
1041 mova [rsp+26*%%str], m14
1042 mova [rsp+30*%%str], m15
1044 ; t0-7 is in [rsp+{0,4,8,12,16,20,24,28}*%%str]
1045 ; t8-15 is in [rsp+{2,6,10,14,18,22,26,30}*%%str]
1046 ; t16-19 and t23 is in [rsp+{1,5,9,13,29}*%%str]
1048 ; t24-31 is in m8-15
1051 %macro %%STORE_2X2 7-8 1 ; src[1-4], tmp[1-2], zero, inc_dst_ptrs
1052 SUMSUB_BA w, %4, %1, %5
1053 SUMSUB_BA w, %3, %2, %5
1054 pmulhrsw m%4, [pw_512]
1055 pmulhrsw m%3, [pw_512]
1056 VP9_STORE_2X %4, %3, %5, %6, %7
1060 pmulhrsw m%2, [pw_512]
1061 pmulhrsw m%1, [pw_512]
1062 VP9_STORE_2X %2, %1, %5, %6, %7, dst_endq
1064 sub dst_endq, stride2q
1068 ; store t0-1 and t30-31
1069 mova m0, [rsp+ 0*%%str]
1070 mova m1, [rsp+ 4*%%str]
1071 %%STORE_2X2 0, 1, 14, 15, 2, 3, 7
1073 ; store t2-3 and t28-29
1074 mova m0, [rsp+ 8*%%str]
1075 mova m1, [rsp+12*%%str]
1076 %%STORE_2X2 0, 1, 12, 13, 2, 3, 7
1078 ; store t4-5 and t26-27
1079 mova m0, [rsp+16*%%str]
1080 mova m1, [rsp+20*%%str]
1081 %%STORE_2X2 0, 1, 10, 11, 2, 3, 7
1083 ; store t6-7 and t24-25
1084 mova m0, [rsp+24*%%str]
1085 mova m1, [rsp+28*%%str]
1086 %%STORE_2X2 0, 1, 8, 9, 2, 3, 7
1088 ; store t8-9 and t22-23
1089 mova m0, [rsp+ 2*%%str]
1090 mova m1, [rsp+ 6*%%str]
1091 mova m8, [rsp+29*%%str]
1092 %%STORE_2X2 0, 1, 6, 8, 2, 3, 7
1094 ; store t10-11 and t20-21
1095 mova m0, [rsp+10*%%str]
1096 mova m1, [rsp+14*%%str]
1097 %%STORE_2X2 0, 1, 4, 5, 2, 3, 7
1099 ; store t12-13 and t18-19
1100 mova m0, [rsp+18*%%str]
1101 mova m1, [rsp+22*%%str]
1102 mova m5, [rsp+13*%%str]
1103 mova m4, [rsp+ 9*%%str]
1104 %%STORE_2X2 0, 1, 4, 5, 2, 3, 7
1107 mova m0, [rsp+26*%%str]
1108 mova m1, [rsp+30*%%str]
1109 mova m5, [rsp+ 5*%%str]
1110 mova m4, [rsp+ 1*%%str]
1111 %%STORE_2X2 0, 1, 4, 5, 2, 3, 7, 0
1115 %macro VP9_IDCT_IDCT_32x32_ADD_XMM 1
1117 cglobal vp9_idct_idct_32x32_add, 4, 8, 16, 2048, dst, stride, block, eob
1127 mova m1, [pw_11585x2]
1130 SPLATW m0, m0, q0000
1131 pmulhrsw m0, [pw_512]
1134 DEFINE_ARGS dst, stride, block, cnt
1136 VP9_STORE_2XFULL 0, 1, 2, 3, 4, 5, mmsize
1139 VP9_STORE_2XFULL 0, 1, 2, 3, 4, 5, mmsize
1142 DEFINE_ARGS dst_bak, stride, block, cnt, dst, stride30, dst_end, stride2
1144 VP9_IDCT32_1D blockq, 1, 8
1146 mov stride30q, strideq ; stride
1147 lea stride2q, [strideq*2] ; stride*2
1148 shl stride30q, 5 ; stride*32
1150 sub stride30q, stride2q ; stride*30
1153 lea dst_endq, [dst_bakq+stride30q]
1154 VP9_IDCT32_1D rsp, 2, 8
1161 ; at the end of the loop, m7 should still be zero
1162 ; use that to zero out block coefficients
1163 ZERO_BLOCK blockq, 64, 8, m7
1169 VP9_IDCT32_1D blockq, 1, 16
1177 mov stride30q, strideq ; stride
1178 lea stride2q, [strideq*2] ; stride*2
1179 shl stride30q, 5 ; stride*32
1181 sub stride30q, stride2q ; stride*30
1184 lea dst_endq, [dst_bakq+stride30q]
1185 VP9_IDCT32_1D rsp, 2, 16
1192 ; at the end of the loop, m7 should still be zero
1193 ; use that to zero out block coefficients
1194 ZERO_BLOCK blockq, 64, 16, m7
1200 VP9_IDCT32_1D blockq, 1
1208 mov stride30q, strideq ; stride
1209 lea stride2q, [strideq*2] ; stride*2
1210 shl stride30q, 5 ; stride*32
1212 sub stride30q, stride2q ; stride*30
1215 lea dst_endq, [dst_bakq+stride30q]
1216 VP9_IDCT32_1D rsp, 2
1223 ; at the end of the loop, m7 should still be zero
1224 ; use that to zero out block coefficients
1225 ZERO_BLOCK blockq, 64, 32, m7
1229 VP9_IDCT_IDCT_32x32_ADD_XMM ssse3
1230 VP9_IDCT_IDCT_32x32_ADD_XMM avx