2 * H.264/HEVC hardware encoding using nvidia nvenc
3 * Copyright (c) 2016 Timo Rothenpieler <timo@rothenpieler.org>
5 * This file is part of FFmpeg.
7 * FFmpeg is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * FFmpeg is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with FFmpeg; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
26 #include "libavutil/hwcontext_cuda.h"
27 #include "libavutil/hwcontext.h"
28 #include "libavutil/imgutils.h"
29 #include "libavutil/avassert.h"
30 #include "libavutil/mem.h"
31 #include "libavutil/pixdesc.h"
34 #define NVENC_CAP 0x30
35 #define IS_CBR(rc) (rc == NV_ENC_PARAMS_RC_CBR || \
36 rc == NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ || \
37 rc == NV_ENC_PARAMS_RC_CBR_HQ)
39 const enum AVPixelFormat ff_nvenc_pix_fmts[] = {
51 #define IS_10BIT(pix_fmt) (pix_fmt == AV_PIX_FMT_P010 || \
52 pix_fmt == AV_PIX_FMT_YUV444P16)
54 #define IS_YUV444(pix_fmt) (pix_fmt == AV_PIX_FMT_YUV444P || \
55 pix_fmt == AV_PIX_FMT_YUV444P16)
62 { NV_ENC_SUCCESS, 0, "success" },
63 { NV_ENC_ERR_NO_ENCODE_DEVICE, AVERROR(ENOENT), "no encode device" },
64 { NV_ENC_ERR_UNSUPPORTED_DEVICE, AVERROR(ENOSYS), "unsupported device" },
65 { NV_ENC_ERR_INVALID_ENCODERDEVICE, AVERROR(EINVAL), "invalid encoder device" },
66 { NV_ENC_ERR_INVALID_DEVICE, AVERROR(EINVAL), "invalid device" },
67 { NV_ENC_ERR_DEVICE_NOT_EXIST, AVERROR(EIO), "device does not exist" },
68 { NV_ENC_ERR_INVALID_PTR, AVERROR(EFAULT), "invalid ptr" },
69 { NV_ENC_ERR_INVALID_EVENT, AVERROR(EINVAL), "invalid event" },
70 { NV_ENC_ERR_INVALID_PARAM, AVERROR(EINVAL), "invalid param" },
71 { NV_ENC_ERR_INVALID_CALL, AVERROR(EINVAL), "invalid call" },
72 { NV_ENC_ERR_OUT_OF_MEMORY, AVERROR(ENOMEM), "out of memory" },
73 { NV_ENC_ERR_ENCODER_NOT_INITIALIZED, AVERROR(EINVAL), "encoder not initialized" },
74 { NV_ENC_ERR_UNSUPPORTED_PARAM, AVERROR(ENOSYS), "unsupported param" },
75 { NV_ENC_ERR_LOCK_BUSY, AVERROR(EAGAIN), "lock busy" },
76 { NV_ENC_ERR_NOT_ENOUGH_BUFFER, AVERROR_BUFFER_TOO_SMALL, "not enough buffer"},
77 { NV_ENC_ERR_INVALID_VERSION, AVERROR(EINVAL), "invalid version" },
78 { NV_ENC_ERR_MAP_FAILED, AVERROR(EIO), "map failed" },
79 { NV_ENC_ERR_NEED_MORE_INPUT, AVERROR(EAGAIN), "need more input" },
80 { NV_ENC_ERR_ENCODER_BUSY, AVERROR(EAGAIN), "encoder busy" },
81 { NV_ENC_ERR_EVENT_NOT_REGISTERD, AVERROR(EBADF), "event not registered" },
82 { NV_ENC_ERR_GENERIC, AVERROR_UNKNOWN, "generic error" },
83 { NV_ENC_ERR_INCOMPATIBLE_CLIENT_KEY, AVERROR(EINVAL), "incompatible client key" },
84 { NV_ENC_ERR_UNIMPLEMENTED, AVERROR(ENOSYS), "unimplemented" },
85 { NV_ENC_ERR_RESOURCE_REGISTER_FAILED, AVERROR(EIO), "resource register failed" },
86 { NV_ENC_ERR_RESOURCE_NOT_REGISTERED, AVERROR(EBADF), "resource not registered" },
87 { NV_ENC_ERR_RESOURCE_NOT_MAPPED, AVERROR(EBADF), "resource not mapped" },
90 static int nvenc_map_error(NVENCSTATUS err, const char **desc)
93 for (i = 0; i < FF_ARRAY_ELEMS(nvenc_errors); i++) {
94 if (nvenc_errors[i].nverr == err) {
96 *desc = nvenc_errors[i].desc;
97 return nvenc_errors[i].averr;
101 *desc = "unknown error";
102 return AVERROR_UNKNOWN;
105 static int nvenc_print_error(void *log_ctx, NVENCSTATUS err,
106 const char *error_string)
110 ret = nvenc_map_error(err, &desc);
111 av_log(log_ctx, AV_LOG_ERROR, "%s: %s (%d)\n", error_string, desc, err);
115 static av_cold int nvenc_load_libraries(AVCodecContext *avctx)
117 NvencContext *ctx = avctx->priv_data;
118 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
120 uint32_t nvenc_max_ver;
123 ret = cuda_load_functions(&dl_fn->cuda_dl);
127 ret = nvenc_load_functions(&dl_fn->nvenc_dl);
131 err = dl_fn->nvenc_dl->NvEncodeAPIGetMaxSupportedVersion(&nvenc_max_ver);
132 if (err != NV_ENC_SUCCESS)
133 return nvenc_print_error(avctx, err, "Failed to query nvenc max version");
135 av_log(avctx, AV_LOG_VERBOSE, "Loaded Nvenc version %d.%d\n", nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
137 if ((NVENCAPI_MAJOR_VERSION << 4 | NVENCAPI_MINOR_VERSION) > nvenc_max_ver) {
138 av_log(avctx, AV_LOG_ERROR, "Driver does not support the required nvenc API version. "
139 "Required: %d.%d Found: %d.%d\n",
140 NVENCAPI_MAJOR_VERSION, NVENCAPI_MINOR_VERSION,
141 nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
142 return AVERROR(ENOSYS);
145 dl_fn->nvenc_funcs.version = NV_ENCODE_API_FUNCTION_LIST_VER;
147 err = dl_fn->nvenc_dl->NvEncodeAPICreateInstance(&dl_fn->nvenc_funcs);
148 if (err != NV_ENC_SUCCESS)
149 return nvenc_print_error(avctx, err, "Failed to create nvenc instance");
151 av_log(avctx, AV_LOG_VERBOSE, "Nvenc initialized successfully\n");
156 static av_cold int nvenc_open_session(AVCodecContext *avctx)
158 NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS params = { 0 };
159 NvencContext *ctx = avctx->priv_data;
160 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
163 params.version = NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS_VER;
164 params.apiVersion = NVENCAPI_VERSION;
165 params.device = ctx->cu_context;
166 params.deviceType = NV_ENC_DEVICE_TYPE_CUDA;
168 ret = p_nvenc->nvEncOpenEncodeSessionEx(¶ms, &ctx->nvencoder);
169 if (ret != NV_ENC_SUCCESS) {
170 ctx->nvencoder = NULL;
171 return nvenc_print_error(avctx, ret, "OpenEncodeSessionEx failed");
177 static int nvenc_check_codec_support(AVCodecContext *avctx)
179 NvencContext *ctx = avctx->priv_data;
180 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
181 int i, ret, count = 0;
184 ret = p_nvenc->nvEncGetEncodeGUIDCount(ctx->nvencoder, &count);
186 if (ret != NV_ENC_SUCCESS || !count)
187 return AVERROR(ENOSYS);
189 guids = av_malloc(count * sizeof(GUID));
191 return AVERROR(ENOMEM);
193 ret = p_nvenc->nvEncGetEncodeGUIDs(ctx->nvencoder, guids, count, &count);
194 if (ret != NV_ENC_SUCCESS) {
195 ret = AVERROR(ENOSYS);
199 ret = AVERROR(ENOSYS);
200 for (i = 0; i < count; i++) {
201 if (!memcmp(&guids[i], &ctx->init_encode_params.encodeGUID, sizeof(*guids))) {
213 static int nvenc_check_cap(AVCodecContext *avctx, NV_ENC_CAPS cap)
215 NvencContext *ctx = avctx->priv_data;
216 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
217 NV_ENC_CAPS_PARAM params = { 0 };
220 params.version = NV_ENC_CAPS_PARAM_VER;
221 params.capsToQuery = cap;
223 ret = p_nvenc->nvEncGetEncodeCaps(ctx->nvencoder, ctx->init_encode_params.encodeGUID, ¶ms, &val);
225 if (ret == NV_ENC_SUCCESS)
230 static int nvenc_check_capabilities(AVCodecContext *avctx)
232 NvencContext *ctx = avctx->priv_data;
235 ret = nvenc_check_codec_support(avctx);
237 av_log(avctx, AV_LOG_VERBOSE, "Codec not supported\n");
241 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_YUV444_ENCODE);
242 if (IS_YUV444(ctx->data_pix_fmt) && ret <= 0) {
243 av_log(avctx, AV_LOG_VERBOSE, "YUV444P not supported\n");
244 return AVERROR(ENOSYS);
247 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOSSLESS_ENCODE);
248 if (ctx->preset >= PRESET_LOSSLESS_DEFAULT && ret <= 0) {
249 av_log(avctx, AV_LOG_VERBOSE, "Lossless encoding not supported\n");
250 return AVERROR(ENOSYS);
253 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_WIDTH_MAX);
254 if (ret < avctx->width) {
255 av_log(avctx, AV_LOG_VERBOSE, "Width %d exceeds %d\n",
257 return AVERROR(ENOSYS);
260 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_HEIGHT_MAX);
261 if (ret < avctx->height) {
262 av_log(avctx, AV_LOG_VERBOSE, "Height %d exceeds %d\n",
264 return AVERROR(ENOSYS);
267 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_NUM_MAX_BFRAMES);
268 if (ret < avctx->max_b_frames) {
269 av_log(avctx, AV_LOG_VERBOSE, "Max B-frames %d exceed %d\n",
270 avctx->max_b_frames, ret);
272 return AVERROR(ENOSYS);
275 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_FIELD_ENCODING);
276 if (ret < 1 && avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
277 av_log(avctx, AV_LOG_VERBOSE,
278 "Interlaced encoding is not supported. Supported level: %d\n",
280 return AVERROR(ENOSYS);
283 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_10BIT_ENCODE);
284 if (IS_10BIT(ctx->data_pix_fmt) && ret <= 0) {
285 av_log(avctx, AV_LOG_VERBOSE, "10 bit encode not supported\n");
286 return AVERROR(ENOSYS);
289 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOOKAHEAD);
290 if (ctx->rc_lookahead > 0 && ret <= 0) {
291 av_log(avctx, AV_LOG_VERBOSE, "RC lookahead not supported\n");
292 return AVERROR(ENOSYS);
295 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_TEMPORAL_AQ);
296 if (ctx->temporal_aq > 0 && ret <= 0) {
297 av_log(avctx, AV_LOG_VERBOSE, "Temporal AQ not supported\n");
298 return AVERROR(ENOSYS);
304 static av_cold int nvenc_check_device(AVCodecContext *avctx, int idx)
306 NvencContext *ctx = avctx->priv_data;
307 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
308 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
309 char name[128] = { 0};
310 int major, minor, ret;
314 int loglevel = AV_LOG_VERBOSE;
316 if (ctx->device == LIST_DEVICES)
317 loglevel = AV_LOG_INFO;
319 cu_res = dl_fn->cuda_dl->cuDeviceGet(&cu_device, idx);
320 if (cu_res != CUDA_SUCCESS) {
321 av_log(avctx, AV_LOG_ERROR,
322 "Cannot access the CUDA device %d\n",
327 cu_res = dl_fn->cuda_dl->cuDeviceGetName(name, sizeof(name), cu_device);
328 if (cu_res != CUDA_SUCCESS) {
329 av_log(avctx, AV_LOG_ERROR, "cuDeviceGetName failed on device %d\n", idx);
333 cu_res = dl_fn->cuda_dl->cuDeviceComputeCapability(&major, &minor, cu_device);
334 if (cu_res != CUDA_SUCCESS) {
335 av_log(avctx, AV_LOG_ERROR, "cuDeviceComputeCapability failed on device %d\n", idx);
339 av_log(avctx, loglevel, "[ GPU #%d - < %s > has Compute SM %d.%d ]\n", idx, name, major, minor);
340 if (((major << 4) | minor) < NVENC_CAP) {
341 av_log(avctx, loglevel, "does not support NVENC\n");
345 if (ctx->device != idx && ctx->device != ANY_DEVICE)
348 cu_res = dl_fn->cuda_dl->cuCtxCreate(&ctx->cu_context_internal, 0, cu_device);
349 if (cu_res != CUDA_SUCCESS) {
350 av_log(avctx, AV_LOG_FATAL, "Failed creating CUDA context for NVENC: 0x%x\n", (int)cu_res);
354 ctx->cu_context = ctx->cu_context_internal;
356 cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
357 if (cu_res != CUDA_SUCCESS) {
358 av_log(avctx, AV_LOG_FATAL, "Failed popping CUDA context: 0x%x\n", (int)cu_res);
362 if ((ret = nvenc_open_session(avctx)) < 0)
365 if ((ret = nvenc_check_capabilities(avctx)) < 0)
368 av_log(avctx, loglevel, "supports NVENC\n");
370 dl_fn->nvenc_device_count++;
372 if (ctx->device == idx || ctx->device == ANY_DEVICE)
376 p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
377 ctx->nvencoder = NULL;
380 dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal);
381 ctx->cu_context_internal = NULL;
384 return AVERROR(ENOSYS);
387 static av_cold int nvenc_setup_device(AVCodecContext *avctx)
389 NvencContext *ctx = avctx->priv_data;
390 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
392 switch (avctx->codec->id) {
393 case AV_CODEC_ID_H264:
394 ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_H264_GUID;
396 case AV_CODEC_ID_HEVC:
397 ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_HEVC_GUID;
403 if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->hw_frames_ctx || avctx->hw_device_ctx) {
404 AVHWFramesContext *frames_ctx;
405 AVHWDeviceContext *hwdev_ctx;
406 AVCUDADeviceContext *device_hwctx;
409 if (avctx->hw_frames_ctx) {
410 frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
411 device_hwctx = frames_ctx->device_ctx->hwctx;
412 } else if (avctx->hw_device_ctx) {
413 hwdev_ctx = (AVHWDeviceContext*)avctx->hw_device_ctx->data;
414 device_hwctx = hwdev_ctx->hwctx;
416 return AVERROR(EINVAL);
419 ctx->cu_context = device_hwctx->cuda_ctx;
421 ret = nvenc_open_session(avctx);
425 ret = nvenc_check_capabilities(avctx);
427 av_log(avctx, AV_LOG_FATAL, "Provided device doesn't support required NVENC features\n");
431 int i, nb_devices = 0;
433 if ((dl_fn->cuda_dl->cuInit(0)) != CUDA_SUCCESS) {
434 av_log(avctx, AV_LOG_ERROR,
435 "Cannot init CUDA\n");
436 return AVERROR_UNKNOWN;
439 if ((dl_fn->cuda_dl->cuDeviceGetCount(&nb_devices)) != CUDA_SUCCESS) {
440 av_log(avctx, AV_LOG_ERROR,
441 "Cannot enumerate the CUDA devices\n");
442 return AVERROR_UNKNOWN;
446 av_log(avctx, AV_LOG_FATAL, "No CUDA capable devices found\n");
447 return AVERROR_EXTERNAL;
450 av_log(avctx, AV_LOG_VERBOSE, "%d CUDA capable devices found\n", nb_devices);
452 dl_fn->nvenc_device_count = 0;
453 for (i = 0; i < nb_devices; ++i) {
454 if ((nvenc_check_device(avctx, i)) >= 0 && ctx->device != LIST_DEVICES)
458 if (ctx->device == LIST_DEVICES)
461 if (!dl_fn->nvenc_device_count) {
462 av_log(avctx, AV_LOG_FATAL, "No NVENC capable devices found\n");
463 return AVERROR_EXTERNAL;
466 av_log(avctx, AV_LOG_FATAL, "Requested GPU %d, but only %d GPUs are available!\n", ctx->device, nb_devices);
467 return AVERROR(EINVAL);
473 typedef struct GUIDTuple {
478 #define PRESET_ALIAS(alias, name, ...) \
479 [PRESET_ ## alias] = { NV_ENC_PRESET_ ## name ## _GUID, __VA_ARGS__ }
481 #define PRESET(name, ...) PRESET_ALIAS(name, name, __VA_ARGS__)
483 static void nvenc_map_preset(NvencContext *ctx)
485 GUIDTuple presets[] = {
490 PRESET_ALIAS(SLOW, HQ, NVENC_TWO_PASSES),
491 PRESET_ALIAS(MEDIUM, HQ, NVENC_ONE_PASS),
492 PRESET_ALIAS(FAST, HP, NVENC_ONE_PASS),
493 PRESET(LOW_LATENCY_DEFAULT, NVENC_LOWLATENCY),
494 PRESET(LOW_LATENCY_HP, NVENC_LOWLATENCY),
495 PRESET(LOW_LATENCY_HQ, NVENC_LOWLATENCY),
496 PRESET(LOSSLESS_DEFAULT, NVENC_LOSSLESS),
497 PRESET(LOSSLESS_HP, NVENC_LOSSLESS),
500 GUIDTuple *t = &presets[ctx->preset];
502 ctx->init_encode_params.presetGUID = t->guid;
503 ctx->flags = t->flags;
509 static av_cold void set_constqp(AVCodecContext *avctx)
511 NvencContext *ctx = avctx->priv_data;
512 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
514 rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
516 if (ctx->init_qp_p >= 0) {
517 rc->constQP.qpInterP = ctx->init_qp_p;
518 if (ctx->init_qp_i >= 0 && ctx->init_qp_b >= 0) {
519 rc->constQP.qpIntra = ctx->init_qp_i;
520 rc->constQP.qpInterB = ctx->init_qp_b;
521 } else if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
522 rc->constQP.qpIntra = av_clip(
523 rc->constQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, 51);
524 rc->constQP.qpInterB = av_clip(
525 rc->constQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, 51);
527 rc->constQP.qpIntra = rc->constQP.qpInterP;
528 rc->constQP.qpInterB = rc->constQP.qpInterP;
530 } else if (ctx->cqp >= 0) {
531 rc->constQP.qpInterP = rc->constQP.qpInterB = rc->constQP.qpIntra = ctx->cqp;
532 if (avctx->b_quant_factor != 0.0)
533 rc->constQP.qpInterB = av_clip(ctx->cqp * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, 51);
534 if (avctx->i_quant_factor != 0.0)
535 rc->constQP.qpIntra = av_clip(ctx->cqp * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, 51);
542 static av_cold void set_vbr(AVCodecContext *avctx)
544 NvencContext *ctx = avctx->priv_data;
545 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
548 if (avctx->qmin >= 0 && avctx->qmax >= 0) {
552 rc->minQP.qpInterB = avctx->qmin;
553 rc->minQP.qpInterP = avctx->qmin;
554 rc->minQP.qpIntra = avctx->qmin;
556 rc->maxQP.qpInterB = avctx->qmax;
557 rc->maxQP.qpInterP = avctx->qmax;
558 rc->maxQP.qpIntra = avctx->qmax;
560 qp_inter_p = (avctx->qmax + 3 * avctx->qmin) / 4; // biased towards Qmin
561 } else if (avctx->qmin >= 0) {
564 rc->minQP.qpInterB = avctx->qmin;
565 rc->minQP.qpInterP = avctx->qmin;
566 rc->minQP.qpIntra = avctx->qmin;
568 qp_inter_p = avctx->qmin;
570 qp_inter_p = 26; // default to 26
573 rc->enableInitialRCQP = 1;
575 if (ctx->init_qp_p < 0) {
576 rc->initialRCQP.qpInterP = qp_inter_p;
578 rc->initialRCQP.qpInterP = ctx->init_qp_p;
581 if (ctx->init_qp_i < 0) {
582 if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
583 rc->initialRCQP.qpIntra = av_clip(
584 rc->initialRCQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, 51);
586 rc->initialRCQP.qpIntra = rc->initialRCQP.qpInterP;
589 rc->initialRCQP.qpIntra = ctx->init_qp_i;
592 if (ctx->init_qp_b < 0) {
593 if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
594 rc->initialRCQP.qpInterB = av_clip(
595 rc->initialRCQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, 51);
597 rc->initialRCQP.qpInterB = rc->initialRCQP.qpInterP;
600 rc->initialRCQP.qpInterB = ctx->init_qp_b;
604 static av_cold void set_lossless(AVCodecContext *avctx)
606 NvencContext *ctx = avctx->priv_data;
607 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
609 rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
610 rc->constQP.qpInterB = 0;
611 rc->constQP.qpInterP = 0;
612 rc->constQP.qpIntra = 0;
618 static void nvenc_override_rate_control(AVCodecContext *avctx)
620 NvencContext *ctx = avctx->priv_data;
621 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
624 case NV_ENC_PARAMS_RC_CONSTQP:
627 case NV_ENC_PARAMS_RC_VBR_MINQP:
628 if (avctx->qmin < 0) {
629 av_log(avctx, AV_LOG_WARNING,
630 "The variable bitrate rate-control requires "
631 "the 'qmin' option set.\n");
636 case NV_ENC_PARAMS_RC_VBR_HQ:
637 case NV_ENC_PARAMS_RC_VBR:
640 case NV_ENC_PARAMS_RC_CBR:
641 case NV_ENC_PARAMS_RC_CBR_HQ:
642 case NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ:
646 rc->rateControlMode = ctx->rc;
649 static av_cold int nvenc_recalc_surfaces(AVCodecContext *avctx)
651 NvencContext *ctx = avctx->priv_data;
652 // default minimum of 4 surfaces
653 // multiply by 2 for number of NVENCs on gpu (hardcode to 2)
654 // another multiply by 2 to avoid blocking next PBB group
655 int nb_surfaces = FFMAX(4, ctx->encode_config.frameIntervalP * 2 * 2);
658 if (ctx->rc_lookahead > 0) {
659 // +1 is to account for lkd_bound calculation later
660 // +4 is to allow sufficient pipelining with lookahead
661 nb_surfaces = FFMAX(1, FFMAX(nb_surfaces, ctx->rc_lookahead + ctx->encode_config.frameIntervalP + 1 + 4));
662 if (nb_surfaces > ctx->nb_surfaces && ctx->nb_surfaces > 0)
664 av_log(avctx, AV_LOG_WARNING,
665 "Defined rc_lookahead requires more surfaces, "
666 "increasing used surfaces %d -> %d\n", ctx->nb_surfaces, nb_surfaces);
668 ctx->nb_surfaces = FFMAX(nb_surfaces, ctx->nb_surfaces);
670 if (ctx->encode_config.frameIntervalP > 1 && ctx->nb_surfaces < nb_surfaces && ctx->nb_surfaces > 0)
672 av_log(avctx, AV_LOG_WARNING,
673 "Defined b-frame requires more surfaces, "
674 "increasing used surfaces %d -> %d\n", ctx->nb_surfaces, nb_surfaces);
675 ctx->nb_surfaces = FFMAX(ctx->nb_surfaces, nb_surfaces);
677 else if (ctx->nb_surfaces <= 0)
678 ctx->nb_surfaces = nb_surfaces;
679 // otherwise use user specified value
682 ctx->nb_surfaces = FFMAX(1, FFMIN(MAX_REGISTERED_FRAMES, ctx->nb_surfaces));
683 ctx->async_depth = FFMIN(ctx->async_depth, ctx->nb_surfaces - 1);
688 static av_cold void nvenc_setup_rate_control(AVCodecContext *avctx)
690 NvencContext *ctx = avctx->priv_data;
692 if (avctx->global_quality > 0)
693 av_log(avctx, AV_LOG_WARNING, "Using global_quality with nvenc is deprecated. Use qp instead.\n");
695 if (ctx->cqp < 0 && avctx->global_quality > 0)
696 ctx->cqp = avctx->global_quality;
698 if (avctx->bit_rate > 0) {
699 ctx->encode_config.rcParams.averageBitRate = avctx->bit_rate;
700 } else if (ctx->encode_config.rcParams.averageBitRate > 0) {
701 ctx->encode_config.rcParams.maxBitRate = ctx->encode_config.rcParams.averageBitRate;
704 if (avctx->rc_max_rate > 0)
705 ctx->encode_config.rcParams.maxBitRate = avctx->rc_max_rate;
708 if (ctx->flags & NVENC_ONE_PASS)
710 if (ctx->flags & NVENC_TWO_PASSES)
713 if (ctx->twopass < 0)
714 ctx->twopass = (ctx->flags & NVENC_LOWLATENCY) != 0;
718 ctx->rc = NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ;
720 ctx->rc = NV_ENC_PARAMS_RC_CBR;
722 } else if (ctx->cqp >= 0) {
723 ctx->rc = NV_ENC_PARAMS_RC_CONSTQP;
724 } else if (ctx->twopass) {
725 ctx->rc = NV_ENC_PARAMS_RC_VBR_HQ;
726 } else if (avctx->qmin >= 0 && avctx->qmax >= 0) {
727 ctx->rc = NV_ENC_PARAMS_RC_VBR_MINQP;
731 if (ctx->rc >= 0 && ctx->rc & RC_MODE_DEPRECATED) {
732 av_log(avctx, AV_LOG_WARNING, "Specified rc mode is deprecated.\n");
733 av_log(avctx, AV_LOG_WARNING, "\tll_2pass_quality -> cbr_ld_hq\n");
734 av_log(avctx, AV_LOG_WARNING, "\tll_2pass_size -> cbr_hq\n");
735 av_log(avctx, AV_LOG_WARNING, "\tvbr_2pass -> vbr_hq\n");
736 av_log(avctx, AV_LOG_WARNING, "\tvbr_minqp -> (no replacement)\n");
738 ctx->rc &= ~RC_MODE_DEPRECATED;
741 if (ctx->flags & NVENC_LOSSLESS) {
743 } else if (ctx->rc >= 0) {
744 nvenc_override_rate_control(avctx);
746 ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_VBR;
750 if (avctx->rc_buffer_size > 0) {
751 ctx->encode_config.rcParams.vbvBufferSize = avctx->rc_buffer_size;
752 } else if (ctx->encode_config.rcParams.averageBitRate > 0) {
753 ctx->encode_config.rcParams.vbvBufferSize = 2 * ctx->encode_config.rcParams.averageBitRate;
757 ctx->encode_config.rcParams.enableAQ = 1;
758 ctx->encode_config.rcParams.aqStrength = ctx->aq_strength;
759 av_log(avctx, AV_LOG_VERBOSE, "AQ enabled.\n");
762 if (ctx->temporal_aq) {
763 ctx->encode_config.rcParams.enableTemporalAQ = 1;
764 av_log(avctx, AV_LOG_VERBOSE, "Temporal AQ enabled.\n");
767 if (ctx->rc_lookahead > 0) {
768 int lkd_bound = FFMIN(ctx->nb_surfaces, ctx->async_depth) -
769 ctx->encode_config.frameIntervalP - 4;
772 av_log(avctx, AV_LOG_WARNING,
773 "Lookahead not enabled. Increase buffer delay (-delay).\n");
775 ctx->encode_config.rcParams.enableLookahead = 1;
776 ctx->encode_config.rcParams.lookaheadDepth = av_clip(ctx->rc_lookahead, 0, lkd_bound);
777 ctx->encode_config.rcParams.disableIadapt = ctx->no_scenecut;
778 ctx->encode_config.rcParams.disableBadapt = !ctx->b_adapt;
779 av_log(avctx, AV_LOG_VERBOSE,
780 "Lookahead enabled: depth %d, scenecut %s, B-adapt %s.\n",
781 ctx->encode_config.rcParams.lookaheadDepth,
782 ctx->encode_config.rcParams.disableIadapt ? "disabled" : "enabled",
783 ctx->encode_config.rcParams.disableBadapt ? "disabled" : "enabled");
787 if (ctx->strict_gop) {
788 ctx->encode_config.rcParams.strictGOPTarget = 1;
789 av_log(avctx, AV_LOG_VERBOSE, "Strict GOP target enabled.\n");
793 ctx->encode_config.rcParams.enableNonRefP = 1;
795 if (ctx->zerolatency)
796 ctx->encode_config.rcParams.zeroReorderDelay = 1;
799 ctx->encode_config.rcParams.targetQuality = ctx->quality;
802 static av_cold int nvenc_setup_h264_config(AVCodecContext *avctx)
804 NvencContext *ctx = avctx->priv_data;
805 NV_ENC_CONFIG *cc = &ctx->encode_config;
806 NV_ENC_CONFIG_H264 *h264 = &cc->encodeCodecConfig.h264Config;
807 NV_ENC_CONFIG_H264_VUI_PARAMETERS *vui = &h264->h264VUIParameters;
809 vui->colourMatrix = avctx->colorspace;
810 vui->colourPrimaries = avctx->color_primaries;
811 vui->transferCharacteristics = avctx->color_trc;
812 vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
813 || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
815 vui->colourDescriptionPresentFlag =
816 (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
818 vui->videoSignalTypePresentFlag =
819 (vui->colourDescriptionPresentFlag
820 || vui->videoFormat != 5
821 || vui->videoFullRangeFlag != 0);
824 h264->sliceModeData = 1;
826 h264->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
827 h264->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
828 h264->outputAUD = ctx->aud;
830 if (avctx->refs >= 0) {
831 /* 0 means "let the hardware decide" */
832 h264->maxNumRefFrames = avctx->refs;
834 if (avctx->gop_size >= 0) {
835 h264->idrPeriod = cc->gopLength;
838 if (IS_CBR(cc->rcParams.rateControlMode)) {
839 h264->outputBufferingPeriodSEI = 1;
840 h264->outputPictureTimingSEI = 1;
843 if (cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ ||
844 cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_CBR_HQ ||
845 cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_VBR_HQ) {
846 h264->adaptiveTransformMode = NV_ENC_H264_ADAPTIVE_TRANSFORM_ENABLE;
847 h264->fmoMode = NV_ENC_H264_FMO_DISABLE;
850 if (ctx->flags & NVENC_LOSSLESS) {
851 h264->qpPrimeYZeroTransformBypassFlag = 1;
853 switch(ctx->profile) {
854 case NV_ENC_H264_PROFILE_BASELINE:
855 cc->profileGUID = NV_ENC_H264_PROFILE_BASELINE_GUID;
856 avctx->profile = FF_PROFILE_H264_BASELINE;
858 case NV_ENC_H264_PROFILE_MAIN:
859 cc->profileGUID = NV_ENC_H264_PROFILE_MAIN_GUID;
860 avctx->profile = FF_PROFILE_H264_MAIN;
862 case NV_ENC_H264_PROFILE_HIGH:
863 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID;
864 avctx->profile = FF_PROFILE_H264_HIGH;
866 case NV_ENC_H264_PROFILE_HIGH_444P:
867 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
868 avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
873 // force setting profile as high444p if input is AV_PIX_FMT_YUV444P
874 if (ctx->data_pix_fmt == AV_PIX_FMT_YUV444P) {
875 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
876 avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
879 h264->chromaFormatIDC = avctx->profile == FF_PROFILE_H264_HIGH_444_PREDICTIVE ? 3 : 1;
881 h264->level = ctx->level;
886 static av_cold int nvenc_setup_hevc_config(AVCodecContext *avctx)
888 NvencContext *ctx = avctx->priv_data;
889 NV_ENC_CONFIG *cc = &ctx->encode_config;
890 NV_ENC_CONFIG_HEVC *hevc = &cc->encodeCodecConfig.hevcConfig;
891 NV_ENC_CONFIG_HEVC_VUI_PARAMETERS *vui = &hevc->hevcVUIParameters;
893 vui->colourMatrix = avctx->colorspace;
894 vui->colourPrimaries = avctx->color_primaries;
895 vui->transferCharacteristics = avctx->color_trc;
896 vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
897 || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
899 vui->colourDescriptionPresentFlag =
900 (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
902 vui->videoSignalTypePresentFlag =
903 (vui->colourDescriptionPresentFlag
904 || vui->videoFormat != 5
905 || vui->videoFullRangeFlag != 0);
908 hevc->sliceModeData = 1;
910 hevc->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
911 hevc->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
912 hevc->outputAUD = ctx->aud;
914 if (avctx->refs >= 0) {
915 /* 0 means "let the hardware decide" */
916 hevc->maxNumRefFramesInDPB = avctx->refs;
918 if (avctx->gop_size >= 0) {
919 hevc->idrPeriod = cc->gopLength;
922 if (IS_CBR(cc->rcParams.rateControlMode)) {
923 hevc->outputBufferingPeriodSEI = 1;
924 hevc->outputPictureTimingSEI = 1;
927 switch (ctx->profile) {
928 case NV_ENC_HEVC_PROFILE_MAIN:
929 cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN_GUID;
930 avctx->profile = FF_PROFILE_HEVC_MAIN;
932 case NV_ENC_HEVC_PROFILE_MAIN_10:
933 cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
934 avctx->profile = FF_PROFILE_HEVC_MAIN_10;
936 case NV_ENC_HEVC_PROFILE_REXT:
937 cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
938 avctx->profile = FF_PROFILE_HEVC_REXT;
942 // force setting profile as main10 if input is 10 bit
943 if (IS_10BIT(ctx->data_pix_fmt)) {
944 cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
945 avctx->profile = FF_PROFILE_HEVC_MAIN_10;
948 // force setting profile as rext if input is yuv444
949 if (IS_YUV444(ctx->data_pix_fmt)) {
950 cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
951 avctx->profile = FF_PROFILE_HEVC_REXT;
954 hevc->chromaFormatIDC = IS_YUV444(ctx->data_pix_fmt) ? 3 : 1;
956 hevc->pixelBitDepthMinus8 = IS_10BIT(ctx->data_pix_fmt) ? 2 : 0;
958 hevc->level = ctx->level;
960 hevc->tier = ctx->tier;
965 static av_cold int nvenc_setup_codec_config(AVCodecContext *avctx)
967 switch (avctx->codec->id) {
968 case AV_CODEC_ID_H264:
969 return nvenc_setup_h264_config(avctx);
970 case AV_CODEC_ID_HEVC:
971 return nvenc_setup_hevc_config(avctx);
972 /* Earlier switch/case will return if unknown codec is passed. */
978 static av_cold int nvenc_setup_encoder(AVCodecContext *avctx)
980 NvencContext *ctx = avctx->priv_data;
981 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
982 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
984 NV_ENC_PRESET_CONFIG preset_config = { 0 };
985 NVENCSTATUS nv_status = NV_ENC_SUCCESS;
986 AVCPBProperties *cpb_props;
990 ctx->encode_config.version = NV_ENC_CONFIG_VER;
991 ctx->init_encode_params.version = NV_ENC_INITIALIZE_PARAMS_VER;
993 ctx->init_encode_params.encodeHeight = avctx->height;
994 ctx->init_encode_params.encodeWidth = avctx->width;
996 ctx->init_encode_params.encodeConfig = &ctx->encode_config;
998 nvenc_map_preset(ctx);
1000 preset_config.version = NV_ENC_PRESET_CONFIG_VER;
1001 preset_config.presetCfg.version = NV_ENC_CONFIG_VER;
1003 nv_status = p_nvenc->nvEncGetEncodePresetConfig(ctx->nvencoder,
1004 ctx->init_encode_params.encodeGUID,
1005 ctx->init_encode_params.presetGUID,
1007 if (nv_status != NV_ENC_SUCCESS)
1008 return nvenc_print_error(avctx, nv_status, "Cannot get the preset configuration");
1010 memcpy(&ctx->encode_config, &preset_config.presetCfg, sizeof(ctx->encode_config));
1012 ctx->encode_config.version = NV_ENC_CONFIG_VER;
1016 if (avctx->sample_aspect_ratio.num > 0 && avctx->sample_aspect_ratio.den > 0) {
1017 dw*= avctx->sample_aspect_ratio.num;
1018 dh*= avctx->sample_aspect_ratio.den;
1020 av_reduce(&dw, &dh, dw, dh, 1024 * 1024);
1021 ctx->init_encode_params.darHeight = dh;
1022 ctx->init_encode_params.darWidth = dw;
1024 ctx->init_encode_params.frameRateNum = avctx->time_base.den;
1025 ctx->init_encode_params.frameRateDen = avctx->time_base.num * avctx->ticks_per_frame;
1027 ctx->init_encode_params.enableEncodeAsync = 0;
1028 ctx->init_encode_params.enablePTD = 1;
1030 if (ctx->bluray_compat) {
1032 avctx->refs = FFMIN(FFMAX(avctx->refs, 0), 6);
1033 avctx->max_b_frames = FFMIN(avctx->max_b_frames, 3);
1034 switch (avctx->codec->id) {
1035 case AV_CODEC_ID_H264:
1036 /* maximum level depends on used resolution */
1038 case AV_CODEC_ID_HEVC:
1039 ctx->level = NV_ENC_LEVEL_HEVC_51;
1040 ctx->tier = NV_ENC_TIER_HEVC_HIGH;
1045 if (avctx->gop_size > 0) {
1046 if (avctx->max_b_frames >= 0) {
1047 /* 0 is intra-only, 1 is I/P only, 2 is one B-Frame, 3 two B-frames, and so on. */
1048 ctx->encode_config.frameIntervalP = avctx->max_b_frames + 1;
1051 ctx->encode_config.gopLength = avctx->gop_size;
1052 } else if (avctx->gop_size == 0) {
1053 ctx->encode_config.frameIntervalP = 0;
1054 ctx->encode_config.gopLength = 1;
1057 ctx->initial_pts[0] = AV_NOPTS_VALUE;
1058 ctx->initial_pts[1] = AV_NOPTS_VALUE;
1060 nvenc_recalc_surfaces(avctx);
1062 nvenc_setup_rate_control(avctx);
1064 if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
1065 ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD;
1067 ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME;
1070 res = nvenc_setup_codec_config(avctx);
1074 nv_status = p_nvenc->nvEncInitializeEncoder(ctx->nvencoder, &ctx->init_encode_params);
1075 if (nv_status != NV_ENC_SUCCESS) {
1076 return nvenc_print_error(avctx, nv_status, "InitializeEncoder failed");
1079 if (ctx->encode_config.frameIntervalP > 1)
1080 avctx->has_b_frames = 2;
1082 if (ctx->encode_config.rcParams.averageBitRate > 0)
1083 avctx->bit_rate = ctx->encode_config.rcParams.averageBitRate;
1085 cpb_props = ff_add_cpb_side_data(avctx);
1087 return AVERROR(ENOMEM);
1088 cpb_props->max_bitrate = ctx->encode_config.rcParams.maxBitRate;
1089 cpb_props->avg_bitrate = avctx->bit_rate;
1090 cpb_props->buffer_size = ctx->encode_config.rcParams.vbvBufferSize;
1095 static NV_ENC_BUFFER_FORMAT nvenc_map_buffer_format(enum AVPixelFormat pix_fmt)
1098 case AV_PIX_FMT_YUV420P:
1099 return NV_ENC_BUFFER_FORMAT_YV12_PL;
1100 case AV_PIX_FMT_NV12:
1101 return NV_ENC_BUFFER_FORMAT_NV12_PL;
1102 case AV_PIX_FMT_P010:
1103 return NV_ENC_BUFFER_FORMAT_YUV420_10BIT;
1104 case AV_PIX_FMT_YUV444P:
1105 return NV_ENC_BUFFER_FORMAT_YUV444_PL;
1106 case AV_PIX_FMT_YUV444P16:
1107 return NV_ENC_BUFFER_FORMAT_YUV444_10BIT;
1108 case AV_PIX_FMT_0RGB32:
1109 return NV_ENC_BUFFER_FORMAT_ARGB;
1110 case AV_PIX_FMT_0BGR32:
1111 return NV_ENC_BUFFER_FORMAT_ABGR;
1113 return NV_ENC_BUFFER_FORMAT_UNDEFINED;
1117 static av_cold int nvenc_alloc_surface(AVCodecContext *avctx, int idx)
1119 NvencContext *ctx = avctx->priv_data;
1120 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1121 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1122 NvencSurface* tmp_surface = &ctx->surfaces[idx];
1124 NVENCSTATUS nv_status;
1125 NV_ENC_CREATE_BITSTREAM_BUFFER allocOut = { 0 };
1126 allocOut.version = NV_ENC_CREATE_BITSTREAM_BUFFER_VER;
1128 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1129 ctx->surfaces[idx].in_ref = av_frame_alloc();
1130 if (!ctx->surfaces[idx].in_ref)
1131 return AVERROR(ENOMEM);
1133 NV_ENC_CREATE_INPUT_BUFFER allocSurf = { 0 };
1135 ctx->surfaces[idx].format = nvenc_map_buffer_format(ctx->data_pix_fmt);
1136 if (ctx->surfaces[idx].format == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
1137 av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
1138 av_get_pix_fmt_name(ctx->data_pix_fmt));
1139 return AVERROR(EINVAL);
1142 allocSurf.version = NV_ENC_CREATE_INPUT_BUFFER_VER;
1143 allocSurf.width = (avctx->width + 31) & ~31;
1144 allocSurf.height = (avctx->height + 31) & ~31;
1145 allocSurf.bufferFmt = ctx->surfaces[idx].format;
1147 nv_status = p_nvenc->nvEncCreateInputBuffer(ctx->nvencoder, &allocSurf);
1148 if (nv_status != NV_ENC_SUCCESS) {
1149 return nvenc_print_error(avctx, nv_status, "CreateInputBuffer failed");
1152 ctx->surfaces[idx].input_surface = allocSurf.inputBuffer;
1153 ctx->surfaces[idx].width = allocSurf.width;
1154 ctx->surfaces[idx].height = allocSurf.height;
1157 nv_status = p_nvenc->nvEncCreateBitstreamBuffer(ctx->nvencoder, &allocOut);
1158 if (nv_status != NV_ENC_SUCCESS) {
1159 int err = nvenc_print_error(avctx, nv_status, "CreateBitstreamBuffer failed");
1160 if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
1161 p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[idx].input_surface);
1162 av_frame_free(&ctx->surfaces[idx].in_ref);
1166 ctx->surfaces[idx].output_surface = allocOut.bitstreamBuffer;
1167 ctx->surfaces[idx].size = allocOut.size;
1169 av_fifo_generic_write(ctx->unused_surface_queue, &tmp_surface, sizeof(tmp_surface), NULL);
1174 static av_cold int nvenc_setup_surfaces(AVCodecContext *avctx)
1176 NvencContext *ctx = avctx->priv_data;
1179 ctx->surfaces = av_mallocz_array(ctx->nb_surfaces, sizeof(*ctx->surfaces));
1181 return AVERROR(ENOMEM);
1183 ctx->timestamp_list = av_fifo_alloc(ctx->nb_surfaces * sizeof(int64_t));
1184 if (!ctx->timestamp_list)
1185 return AVERROR(ENOMEM);
1187 ctx->unused_surface_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
1188 if (!ctx->unused_surface_queue)
1189 return AVERROR(ENOMEM);
1191 ctx->output_surface_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
1192 if (!ctx->output_surface_queue)
1193 return AVERROR(ENOMEM);
1194 ctx->output_surface_ready_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
1195 if (!ctx->output_surface_ready_queue)
1196 return AVERROR(ENOMEM);
1198 for (i = 0; i < ctx->nb_surfaces; i++) {
1199 if ((res = nvenc_alloc_surface(avctx, i)) < 0)
1206 static av_cold int nvenc_setup_extradata(AVCodecContext *avctx)
1208 NvencContext *ctx = avctx->priv_data;
1209 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1210 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1212 NVENCSTATUS nv_status;
1213 uint32_t outSize = 0;
1214 char tmpHeader[256];
1215 NV_ENC_SEQUENCE_PARAM_PAYLOAD payload = { 0 };
1216 payload.version = NV_ENC_SEQUENCE_PARAM_PAYLOAD_VER;
1218 payload.spsppsBuffer = tmpHeader;
1219 payload.inBufferSize = sizeof(tmpHeader);
1220 payload.outSPSPPSPayloadSize = &outSize;
1222 nv_status = p_nvenc->nvEncGetSequenceParams(ctx->nvencoder, &payload);
1223 if (nv_status != NV_ENC_SUCCESS) {
1224 return nvenc_print_error(avctx, nv_status, "GetSequenceParams failed");
1227 avctx->extradata_size = outSize;
1228 avctx->extradata = av_mallocz(outSize + AV_INPUT_BUFFER_PADDING_SIZE);
1230 if (!avctx->extradata) {
1231 return AVERROR(ENOMEM);
1234 memcpy(avctx->extradata, tmpHeader, outSize);
1239 av_cold int ff_nvenc_encode_close(AVCodecContext *avctx)
1241 NvencContext *ctx = avctx->priv_data;
1242 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1243 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1246 /* the encoder has to be flushed before it can be closed */
1247 if (ctx->nvencoder) {
1248 NV_ENC_PIC_PARAMS params = { .version = NV_ENC_PIC_PARAMS_VER,
1249 .encodePicFlags = NV_ENC_PIC_FLAG_EOS };
1251 p_nvenc->nvEncEncodePicture(ctx->nvencoder, ¶ms);
1254 av_fifo_freep(&ctx->timestamp_list);
1255 av_fifo_freep(&ctx->output_surface_ready_queue);
1256 av_fifo_freep(&ctx->output_surface_queue);
1257 av_fifo_freep(&ctx->unused_surface_queue);
1259 if (ctx->surfaces && avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1260 for (i = 0; i < ctx->nb_surfaces; ++i) {
1261 if (ctx->surfaces[i].input_surface) {
1262 p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, ctx->surfaces[i].in_map.mappedResource);
1265 for (i = 0; i < ctx->nb_registered_frames; i++) {
1266 if (ctx->registered_frames[i].regptr)
1267 p_nvenc->nvEncUnregisterResource(ctx->nvencoder, ctx->registered_frames[i].regptr);
1269 ctx->nb_registered_frames = 0;
1272 if (ctx->surfaces) {
1273 for (i = 0; i < ctx->nb_surfaces; ++i) {
1274 if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
1275 p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[i].input_surface);
1276 av_frame_free(&ctx->surfaces[i].in_ref);
1277 p_nvenc->nvEncDestroyBitstreamBuffer(ctx->nvencoder, ctx->surfaces[i].output_surface);
1280 av_freep(&ctx->surfaces);
1281 ctx->nb_surfaces = 0;
1284 p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
1285 ctx->nvencoder = NULL;
1287 if (ctx->cu_context_internal)
1288 dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal);
1289 ctx->cu_context = ctx->cu_context_internal = NULL;
1291 nvenc_free_functions(&dl_fn->nvenc_dl);
1292 cuda_free_functions(&dl_fn->cuda_dl);
1294 dl_fn->nvenc_device_count = 0;
1296 av_log(avctx, AV_LOG_VERBOSE, "Nvenc unloaded\n");
1301 av_cold int ff_nvenc_encode_init(AVCodecContext *avctx)
1303 NvencContext *ctx = avctx->priv_data;
1306 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1307 AVHWFramesContext *frames_ctx;
1308 if (!avctx->hw_frames_ctx) {
1309 av_log(avctx, AV_LOG_ERROR,
1310 "hw_frames_ctx must be set when using GPU frames as input\n");
1311 return AVERROR(EINVAL);
1313 frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
1314 ctx->data_pix_fmt = frames_ctx->sw_format;
1316 ctx->data_pix_fmt = avctx->pix_fmt;
1319 if ((ret = nvenc_load_libraries(avctx)) < 0)
1322 if ((ret = nvenc_setup_device(avctx)) < 0)
1325 if ((ret = nvenc_setup_encoder(avctx)) < 0)
1328 if ((ret = nvenc_setup_surfaces(avctx)) < 0)
1331 if (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) {
1332 if ((ret = nvenc_setup_extradata(avctx)) < 0)
1339 static NvencSurface *get_free_frame(NvencContext *ctx)
1341 NvencSurface *tmp_surf;
1343 if (!(av_fifo_size(ctx->unused_surface_queue) > 0))
1347 av_fifo_generic_read(ctx->unused_surface_queue, &tmp_surf, sizeof(tmp_surf), NULL);
1351 static int nvenc_copy_frame(AVCodecContext *avctx, NvencSurface *nv_surface,
1352 NV_ENC_LOCK_INPUT_BUFFER *lock_buffer_params, const AVFrame *frame)
1354 int dst_linesize[4] = {
1355 lock_buffer_params->pitch,
1356 lock_buffer_params->pitch,
1357 lock_buffer_params->pitch,
1358 lock_buffer_params->pitch
1360 uint8_t *dst_data[4];
1363 if (frame->format == AV_PIX_FMT_YUV420P)
1364 dst_linesize[1] = dst_linesize[2] >>= 1;
1366 ret = av_image_fill_pointers(dst_data, frame->format, nv_surface->height,
1367 lock_buffer_params->bufferDataPtr, dst_linesize);
1371 if (frame->format == AV_PIX_FMT_YUV420P)
1372 FFSWAP(uint8_t*, dst_data[1], dst_data[2]);
1374 av_image_copy(dst_data, dst_linesize,
1375 (const uint8_t**)frame->data, frame->linesize, frame->format,
1376 avctx->width, avctx->height);
1381 static int nvenc_find_free_reg_resource(AVCodecContext *avctx)
1383 NvencContext *ctx = avctx->priv_data;
1384 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1385 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1389 if (ctx->nb_registered_frames == FF_ARRAY_ELEMS(ctx->registered_frames)) {
1390 for (i = 0; i < ctx->nb_registered_frames; i++) {
1391 if (!ctx->registered_frames[i].mapped) {
1392 if (ctx->registered_frames[i].regptr) {
1393 p_nvenc->nvEncUnregisterResource(ctx->nvencoder,
1394 ctx->registered_frames[i].regptr);
1395 ctx->registered_frames[i].regptr = NULL;
1401 return ctx->nb_registered_frames++;
1404 av_log(avctx, AV_LOG_ERROR, "Too many registered CUDA frames\n");
1405 return AVERROR(ENOMEM);
1408 static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
1410 NvencContext *ctx = avctx->priv_data;
1411 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1412 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1414 AVHWFramesContext *frames_ctx = (AVHWFramesContext*)frame->hw_frames_ctx->data;
1415 NV_ENC_REGISTER_RESOURCE reg;
1418 for (i = 0; i < ctx->nb_registered_frames; i++) {
1419 if (ctx->registered_frames[i].ptr == (CUdeviceptr)frame->data[0])
1423 idx = nvenc_find_free_reg_resource(avctx);
1427 reg.version = NV_ENC_REGISTER_RESOURCE_VER;
1428 reg.resourceType = NV_ENC_INPUT_RESOURCE_TYPE_CUDADEVICEPTR;
1429 reg.width = frames_ctx->width;
1430 reg.height = frames_ctx->height;
1431 reg.pitch = frame->linesize[0];
1432 reg.resourceToRegister = frame->data[0];
1434 reg.bufferFormat = nvenc_map_buffer_format(frames_ctx->sw_format);
1435 if (reg.bufferFormat == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
1436 av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
1437 av_get_pix_fmt_name(frames_ctx->sw_format));
1438 return AVERROR(EINVAL);
1441 ret = p_nvenc->nvEncRegisterResource(ctx->nvencoder, ®);
1442 if (ret != NV_ENC_SUCCESS) {
1443 nvenc_print_error(avctx, ret, "Error registering an input resource");
1444 return AVERROR_UNKNOWN;
1447 ctx->registered_frames[idx].ptr = (CUdeviceptr)frame->data[0];
1448 ctx->registered_frames[idx].regptr = reg.registeredResource;
1452 static int nvenc_upload_frame(AVCodecContext *avctx, const AVFrame *frame,
1453 NvencSurface *nvenc_frame)
1455 NvencContext *ctx = avctx->priv_data;
1456 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1457 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1460 NVENCSTATUS nv_status;
1462 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1463 int reg_idx = nvenc_register_frame(avctx, frame);
1465 av_log(avctx, AV_LOG_ERROR, "Could not register an input CUDA frame\n");
1469 res = av_frame_ref(nvenc_frame->in_ref, frame);
1473 nvenc_frame->in_map.version = NV_ENC_MAP_INPUT_RESOURCE_VER;
1474 nvenc_frame->in_map.registeredResource = ctx->registered_frames[reg_idx].regptr;
1475 nv_status = p_nvenc->nvEncMapInputResource(ctx->nvencoder, &nvenc_frame->in_map);
1476 if (nv_status != NV_ENC_SUCCESS) {
1477 av_frame_unref(nvenc_frame->in_ref);
1478 return nvenc_print_error(avctx, nv_status, "Error mapping an input resource");
1481 ctx->registered_frames[reg_idx].mapped = 1;
1482 nvenc_frame->reg_idx = reg_idx;
1483 nvenc_frame->input_surface = nvenc_frame->in_map.mappedResource;
1484 nvenc_frame->format = nvenc_frame->in_map.mappedBufferFmt;
1485 nvenc_frame->pitch = frame->linesize[0];
1488 NV_ENC_LOCK_INPUT_BUFFER lockBufferParams = { 0 };
1490 lockBufferParams.version = NV_ENC_LOCK_INPUT_BUFFER_VER;
1491 lockBufferParams.inputBuffer = nvenc_frame->input_surface;
1493 nv_status = p_nvenc->nvEncLockInputBuffer(ctx->nvencoder, &lockBufferParams);
1494 if (nv_status != NV_ENC_SUCCESS) {
1495 return nvenc_print_error(avctx, nv_status, "Failed locking nvenc input buffer");
1498 nvenc_frame->pitch = lockBufferParams.pitch;
1499 res = nvenc_copy_frame(avctx, nvenc_frame, &lockBufferParams, frame);
1501 nv_status = p_nvenc->nvEncUnlockInputBuffer(ctx->nvencoder, nvenc_frame->input_surface);
1502 if (nv_status != NV_ENC_SUCCESS) {
1503 return nvenc_print_error(avctx, nv_status, "Failed unlocking input buffer!");
1510 static void nvenc_codec_specific_pic_params(AVCodecContext *avctx,
1511 NV_ENC_PIC_PARAMS *params)
1513 NvencContext *ctx = avctx->priv_data;
1515 switch (avctx->codec->id) {
1516 case AV_CODEC_ID_H264:
1517 params->codecPicParams.h264PicParams.sliceMode =
1518 ctx->encode_config.encodeCodecConfig.h264Config.sliceMode;
1519 params->codecPicParams.h264PicParams.sliceModeData =
1520 ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
1522 case AV_CODEC_ID_HEVC:
1523 params->codecPicParams.hevcPicParams.sliceMode =
1524 ctx->encode_config.encodeCodecConfig.hevcConfig.sliceMode;
1525 params->codecPicParams.hevcPicParams.sliceModeData =
1526 ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
1531 static inline void timestamp_queue_enqueue(AVFifoBuffer* queue, int64_t timestamp)
1533 av_fifo_generic_write(queue, ×tamp, sizeof(timestamp), NULL);
1536 static inline int64_t timestamp_queue_dequeue(AVFifoBuffer* queue)
1538 int64_t timestamp = AV_NOPTS_VALUE;
1539 if (av_fifo_size(queue) > 0)
1540 av_fifo_generic_read(queue, ×tamp, sizeof(timestamp), NULL);
1545 static int nvenc_set_timestamp(AVCodecContext *avctx,
1546 NV_ENC_LOCK_BITSTREAM *params,
1549 NvencContext *ctx = avctx->priv_data;
1551 pkt->pts = params->outputTimeStamp;
1553 /* generate the first dts by linearly extrapolating the
1554 * first two pts values to the past */
1555 if (avctx->max_b_frames > 0 && !ctx->first_packet_output &&
1556 ctx->initial_pts[1] != AV_NOPTS_VALUE) {
1557 int64_t ts0 = ctx->initial_pts[0], ts1 = ctx->initial_pts[1];
1560 if ((ts0 < 0 && ts1 > INT64_MAX + ts0) ||
1561 (ts0 > 0 && ts1 < INT64_MIN + ts0))
1562 return AVERROR(ERANGE);
1565 if ((delta < 0 && ts0 > INT64_MAX + delta) ||
1566 (delta > 0 && ts0 < INT64_MIN + delta))
1567 return AVERROR(ERANGE);
1568 pkt->dts = ts0 - delta;
1570 ctx->first_packet_output = 1;
1574 pkt->dts = timestamp_queue_dequeue(ctx->timestamp_list);
1579 static int process_output_surface(AVCodecContext *avctx, AVPacket *pkt, NvencSurface *tmpoutsurf)
1581 NvencContext *ctx = avctx->priv_data;
1582 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1583 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1585 uint32_t slice_mode_data;
1586 uint32_t *slice_offsets = NULL;
1587 NV_ENC_LOCK_BITSTREAM lock_params = { 0 };
1588 NVENCSTATUS nv_status;
1591 enum AVPictureType pict_type;
1593 switch (avctx->codec->id) {
1594 case AV_CODEC_ID_H264:
1595 slice_mode_data = ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
1597 case AV_CODEC_ID_H265:
1598 slice_mode_data = ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
1601 av_log(avctx, AV_LOG_ERROR, "Unknown codec name\n");
1602 res = AVERROR(EINVAL);
1605 slice_offsets = av_mallocz(slice_mode_data * sizeof(*slice_offsets));
1610 lock_params.version = NV_ENC_LOCK_BITSTREAM_VER;
1612 lock_params.doNotWait = 0;
1613 lock_params.outputBitstream = tmpoutsurf->output_surface;
1614 lock_params.sliceOffsets = slice_offsets;
1616 nv_status = p_nvenc->nvEncLockBitstream(ctx->nvencoder, &lock_params);
1617 if (nv_status != NV_ENC_SUCCESS) {
1618 res = nvenc_print_error(avctx, nv_status, "Failed locking bitstream buffer");
1622 if (res = ff_alloc_packet2(avctx, pkt, lock_params.bitstreamSizeInBytes,0)) {
1623 p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
1627 memcpy(pkt->data, lock_params.bitstreamBufferPtr, lock_params.bitstreamSizeInBytes);
1629 nv_status = p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
1630 if (nv_status != NV_ENC_SUCCESS)
1631 nvenc_print_error(avctx, nv_status, "Failed unlocking bitstream buffer, expect the gates of mordor to open");
1634 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1635 p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, tmpoutsurf->in_map.mappedResource);
1636 av_frame_unref(tmpoutsurf->in_ref);
1637 ctx->registered_frames[tmpoutsurf->reg_idx].mapped = 0;
1639 tmpoutsurf->input_surface = NULL;
1642 switch (lock_params.pictureType) {
1643 case NV_ENC_PIC_TYPE_IDR:
1644 pkt->flags |= AV_PKT_FLAG_KEY;
1645 case NV_ENC_PIC_TYPE_I:
1646 pict_type = AV_PICTURE_TYPE_I;
1648 case NV_ENC_PIC_TYPE_P:
1649 pict_type = AV_PICTURE_TYPE_P;
1651 case NV_ENC_PIC_TYPE_B:
1652 pict_type = AV_PICTURE_TYPE_B;
1654 case NV_ENC_PIC_TYPE_BI:
1655 pict_type = AV_PICTURE_TYPE_BI;
1658 av_log(avctx, AV_LOG_ERROR, "Unknown picture type encountered, expect the output to be broken.\n");
1659 av_log(avctx, AV_LOG_ERROR, "Please report this error and include as much information on how to reproduce it as possible.\n");
1660 res = AVERROR_EXTERNAL;
1664 #if FF_API_CODED_FRAME
1665 FF_DISABLE_DEPRECATION_WARNINGS
1666 avctx->coded_frame->pict_type = pict_type;
1667 FF_ENABLE_DEPRECATION_WARNINGS
1670 ff_side_data_set_encoder_stats(pkt,
1671 (lock_params.frameAvgQP - 1) * FF_QP2LAMBDA, NULL, 0, pict_type);
1673 res = nvenc_set_timestamp(avctx, &lock_params, pkt);
1677 av_free(slice_offsets);
1682 timestamp_queue_dequeue(ctx->timestamp_list);
1685 av_free(slice_offsets);
1690 static int output_ready(AVCodecContext *avctx, int flush)
1692 NvencContext *ctx = avctx->priv_data;
1693 int nb_ready, nb_pending;
1695 /* when B-frames are enabled, we wait for two initial timestamps to
1696 * calculate the first dts */
1697 if (!flush && avctx->max_b_frames > 0 &&
1698 (ctx->initial_pts[0] == AV_NOPTS_VALUE || ctx->initial_pts[1] == AV_NOPTS_VALUE))
1701 nb_ready = av_fifo_size(ctx->output_surface_ready_queue) / sizeof(NvencSurface*);
1702 nb_pending = av_fifo_size(ctx->output_surface_queue) / sizeof(NvencSurface*);
1704 return nb_ready > 0;
1705 return (nb_ready > 0) && (nb_ready + nb_pending >= ctx->async_depth);
1708 int ff_nvenc_encode_frame(AVCodecContext *avctx, AVPacket *pkt,
1709 const AVFrame *frame, int *got_packet)
1711 NVENCSTATUS nv_status;
1714 NvencSurface *tmpoutsurf, *inSurf;
1717 NvencContext *ctx = avctx->priv_data;
1718 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1719 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1721 NV_ENC_PIC_PARAMS pic_params = { 0 };
1722 pic_params.version = NV_ENC_PIC_PARAMS_VER;
1725 inSurf = get_free_frame(ctx);
1727 av_log(avctx, AV_LOG_ERROR, "No free surfaces\n");
1731 cu_res = dl_fn->cuda_dl->cuCtxPushCurrent(ctx->cu_context);
1732 if (cu_res != CUDA_SUCCESS) {
1733 av_log(avctx, AV_LOG_ERROR, "cuCtxPushCurrent failed\n");
1734 return AVERROR_EXTERNAL;
1737 res = nvenc_upload_frame(avctx, frame, inSurf);
1739 cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
1740 if (cu_res != CUDA_SUCCESS) {
1741 av_log(avctx, AV_LOG_ERROR, "cuCtxPopCurrent failed\n");
1742 return AVERROR_EXTERNAL;
1749 pic_params.inputBuffer = inSurf->input_surface;
1750 pic_params.bufferFmt = inSurf->format;
1751 pic_params.inputWidth = avctx->width;
1752 pic_params.inputHeight = avctx->height;
1753 pic_params.inputPitch = inSurf->pitch;
1754 pic_params.outputBitstream = inSurf->output_surface;
1756 if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
1757 if (frame->top_field_first)
1758 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM;
1760 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP;
1762 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FRAME;
1765 if (ctx->forced_idr >= 0 && frame->pict_type == AV_PICTURE_TYPE_I) {
1766 pic_params.encodePicFlags =
1767 ctx->forced_idr ? NV_ENC_PIC_FLAG_FORCEIDR : NV_ENC_PIC_FLAG_FORCEINTRA;
1769 pic_params.encodePicFlags = 0;
1772 pic_params.inputTimeStamp = frame->pts;
1774 nvenc_codec_specific_pic_params(avctx, &pic_params);
1776 pic_params.encodePicFlags = NV_ENC_PIC_FLAG_EOS;
1779 cu_res = dl_fn->cuda_dl->cuCtxPushCurrent(ctx->cu_context);
1780 if (cu_res != CUDA_SUCCESS) {
1781 av_log(avctx, AV_LOG_ERROR, "cuCtxPushCurrent failed\n");
1782 return AVERROR_EXTERNAL;
1785 nv_status = p_nvenc->nvEncEncodePicture(ctx->nvencoder, &pic_params);
1787 cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
1788 if (cu_res != CUDA_SUCCESS) {
1789 av_log(avctx, AV_LOG_ERROR, "cuCtxPopCurrent failed\n");
1790 return AVERROR_EXTERNAL;
1793 if (nv_status != NV_ENC_SUCCESS &&
1794 nv_status != NV_ENC_ERR_NEED_MORE_INPUT)
1795 return nvenc_print_error(avctx, nv_status, "EncodePicture failed!");
1798 av_fifo_generic_write(ctx->output_surface_queue, &inSurf, sizeof(inSurf), NULL);
1799 timestamp_queue_enqueue(ctx->timestamp_list, frame->pts);
1801 if (ctx->initial_pts[0] == AV_NOPTS_VALUE)
1802 ctx->initial_pts[0] = frame->pts;
1803 else if (ctx->initial_pts[1] == AV_NOPTS_VALUE)
1804 ctx->initial_pts[1] = frame->pts;
1807 /* all the pending buffers are now ready for output */
1808 if (nv_status == NV_ENC_SUCCESS) {
1809 while (av_fifo_size(ctx->output_surface_queue) > 0) {
1810 av_fifo_generic_read(ctx->output_surface_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1811 av_fifo_generic_write(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1815 if (output_ready(avctx, !frame)) {
1816 av_fifo_generic_read(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1818 res = process_output_surface(avctx, pkt, tmpoutsurf);
1823 av_fifo_generic_write(ctx->unused_surface_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);